ADC questions on PCM system

ADC questions

I was going through an old exam paper to practice for an upcoming exam and I had a question on a PCM system. I know how a PCM system works but the questions are a little about my head:

The ADC has the following spec:
Resolution - 10 bits
Conversion Rate - 2 micro seconds
Input Voltage Range - 0V-5V
Power Dissipation - 875mV


1. Calculate the quantisation error for the ADC.

2. What is the binary number at the output of the ADC when the input voltage is 0.2V?

3. Clock A (clock leading into the sampling gate) has a frequency of 6kHz and Clock B (clock leading into PISO register) has a frequency of 1MHz.

a) What is the highest analogue input frequency which the system can reliably handle?

b) How long does iut take the PISO register to output one 10 bit sample from the ADC?

c) Calculate the period of clock A.

d) Use your answers from b) and c) to calculate how many PCM transmitters identical to the one in this question could be combined using TDM onto one communication link.

Not too sure on any of them or how to do them.

Also have on question on a simple radio receiver.

I have an inductor rated at 10mH and a variable capacitor set at 40pF.
Calculate the resonant frequency of the tuned circuit.





Thanks for any help.

Re: ADC questions

Hi Kris,
on the fly I can answer question 2. You have a 10 bit resolution that means 2 in the power of 9 ( binary: 2x1+2x2+2x4+....+2x512=1023 ==>1111111111 max value) or 1024 different combinations. That means that 1 bit represents the analog value of 5V /1024= 0.02441 V is your sensitivity. so if you now measure 0.2 the output will be 0.2/0.02441 = 8,192 or 00000001000=analog 8 .

Don't get confused with 1023 and 1024. You have 1024 different values and a total of 1023 in decimal count . The 1024th is the number 0 ( it is also a value).

I will check for quantization error because I don't remember the exact definition. It has to do with a ratio of analog value and quantized one ( say 8/8.192 or something like this, but I will check).

Now, regarding the sampling rate you have the Nyquist criterion : The sampling rate can't be higher than the doubled frequency of the sample B=2f. Apply this and you will have your answer.

Since I am replying this during a sort break at work, I can't help you any more. Soon I will also move the dust from my books and I will come back with more info,

Hope I helped ( maybe with gaps in theory... :-D)

D.

ADC questions

Much appreciated. You have helped me quite a bit.

I know that quantization error is basically what is lost of the original signal after ADC. I just have no clue how to work it out. Your help with question 2 may just help me work it out myself though.

I also had a feeling the sampling gate would be twice the frequency.

Thanks for your help.

Anyone else got any advice to help me with the others?

Re: ADC questions

Hi !

Helping you on the tuned LC circuit, the formula is:

Resonant Frequency = 1 / ( 2 * PI * √ (L * C)
What results in: 1 / ( 2 * 3.14159 * (0.010 * 40E-12)^0.5 ) = 251.646 kHz

Good clue for the Quantization Error question is to read the documente "ABCs of ADCs" available at National site. A piece from this article:

"The maximum error we have here is 1 LSB. This 0 to 1 LSB range is known as the “quantization uncertainty” because there are a range of analog input values that could have caused any given code and we are uncertain at to exactly what that input voltage was. The maximum quantization uncertainty is also known as
the “quantization error”. This error results from the finite resolution of the ADC. That is, the ADC can only resolve the input into 2n discrete values. The converter resolution, then, is 2n. So, for an 8 Volt reference (with a unity gain factor), a 3-bit converter resolves the input into VREF/8 = 8V/8 = 1 Volt steps. Quantization error
then is a round off error.

But an error of 0 to 1 LSB is not as desirable as is an error of ±1/2 LSB, so we introduce an offset into the A/D converter to force an error range of ±1/2 LSB.
Digital Output "

Correcting the coleague response:
The binary number at output of AD converter will be: 0000101000 which means 40 in decimal. In fact at 10 bits resolution, you have 1023 steps and 1024 points. The range is 5V - 0V = 5V
Each step has 5V/1023 = 0.00488759V
So 0.2 / 0.00488759 = 40.92 which turns into 40 integer or 0000101000 binary.
Here you can see that the error is 0.92 * 0.00488759 = 4.49mV.
The quantization error can reach 4.88759mV or 1 LSb