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For these circuits, the easy way to analyse them are:
1. Consider the emitters of the BJT to be virtual ground. (not strictly true, but good enough for a simple analysis)
2. For the first case, break the loop at the gate of the NMOS current mirror. Take the scenario, if the gate of the NMOS(non-diode connected) is increased, the NMOS diode in the return path would have its gate increase also. As both of these are in the same direction, positive feedback occurs. However, negative feedback is effected thru the resistor at the source of the NMOS, which would eventually stabilise the circuit to an OP point.
3. For the second case, it's a similar story except that there is no negative feedback for stabilisation.
If you want to calculate the gain, just break the loop at the point mentioned above, inject a signal and carry on with the normal small signal analysis.
First, determine the operating point (hopefully, as the designer, you know the OP that you desired)
You can determine the small signal parameters for each device (transconductance).
The transconductances on the p-channels will be the same in both cases. This means that if you inject a current into the diode connected device, the same current will be seen at the mirror device.
Now, for the combination of n-channels and bipolars:
The transconductance of a bipolar will be gm.b=I*q/KT, and will be the same for both bipolars (as long as the two currents are the same, even with different areas for the two bipolars).
The transconductance of a resistor is gm.r=1/R.
The total transconductance of the mos with bipolar will be 1/(1/gm+KT/Iq).
The total transconductance of the mos with bipolar and resistor will be 1/(1/gm+KT/Iq+R).
In Fig 1, a (small signal) current injected into the diode connected device will produce an output current of (Iq+KTgm)/(Iq+KTgm+R*Iq*gm). This will always be less than 1. When the loop is intact, this will mean that a small current injected into the diode connected device will become a smaller current when mirrored thru the p-channels.
In Fig 2, a current injected into the diode connected device will produce an output current of (Iq+KTgm+R*Iq*gm)/(Iq+KTgm). This will always be greater than 1. If a small current is injected into the diode connected device, it will cause a larger current out, which will be fed thru the p-channels. The little bit of extra current mirrored around will also be injected into the mirror, and will be made larger. The current will continue to increase until something drops the gain (usually one of the devices will go linear) As you can see, positive feedback greater than unity is a problem, and will cause the circuit of fig 2 to not work!
JPR is great in analyzing the circuit, I also learn much in his explanation. and I do some study based on his statement. the attachment is my study, share with all of u.
JPR is great in analyzing the circuit, I also learn much in his explanation. and I do some study based on his statement. the attachment is my study, share with all of u.
You are right philpsu fig 1 is negative feedback and fig 2 is positive feedback.I will explain why
Fist fig 1
I suppose the current is increasing , if the current increases , on the right side the increase in voltage throught the resistor is higher than the left side ( don't forget bipolar have got exponantial law) so now the voltage on the top of the resistor has increase!
But the NMOS are connected as Common gate (cascode here) so the gate of PMOS (cascode mirror) (again on the right side) increases , so the current decrease .
Now tell me why I told you fig2 is a positive feedback
If I helped you please push the buttom helped
Regards
Your (MLR67) analysis is correct, the currrent will decrease around the loop in fig 1. However, since the sign does not change, the feedback is positive feedback.
It seems that you mixed the polarity (sign) of the feedback with the magnitude of the feedback. If the magnitude of the feedback signal is the same sign, but smaller in magnitude, it does not mean negative feedback, but rather means positive feedback with gain less than 1x.
As an example, assume the steady state loop current is 5uA, the nmos transonductances are 0.04mmhos, the bipolar transconductances are 0.2mmho, and the resistor is 10kohms.
Changing the current to 5.1uA into the diode connected nmos of fig 1 will cause a voltage increase of 3mV at the gate of the nmos devices. This increase in gate voltage will cause an increase in current out of the right side to be 5.075uA. This will be mirrored by the PMOS mirror and fed back. Since the fed back signal went from 5uA to 5.075uA, it changed by 0.075uA for a 0.1uA input signal. The sign is the same, so the feedback is POSITIVE. The loop gain in this case will be +0.75.
If the result was that the current around the loop became 4.925uA, or any value less than 5.0uA, THEN the feedback would be negative, but this is not what happens with the circuit given.
You are right JPR concerning the voltage sign , but on this problem , the most important is to have a current constant .In Fig1, there is a conversion current to voltage and this "loop" is negative because if the current increases or decreases the loop bring back the current at this steady state.
You are right philpsu fig 1 is negative feedback and fig 2 is positive feedback.I will explain why
Fist fig 1
I suppose the current is increasing , if the current increases , on the right side the increase in voltage throught the resistor is higher than the left side ( don't forget bipolar have got exponantial law) so now the voltage on the top of the resistor has increase!
But the NMOS are connected as Common gate (cascode here) so the gate of PMOS (cascode mirror) (again on the right side) increases , so the current decrease .
Now tell me why I told you fig2 is a positive feedback
I agree that if the current increases, the voltage on the resistor increases. However, the voltage on the GATE will increase by a larger amount, causing Vgs to increase, current to increase, etc. - **POSITIVE FEEDBACK**
This DOES NOT mean that fig 1 is unstable. In fact I stated in my first reply that it IS stable, and does work properly!
They are both positive feedback.
The difference is that in one case, the gain is greater than unity (unstable) and in the other case, it is less than unity (stable).
If, instead of the loop gain, you are talking about just the impact of the resistor on the single NMOS device, YES, THAT IS negative feedback. There is also negative feedback due to the bipolar. In fact, the local feedback due to the resistor is also negative in Fig 2. IT is the loop gain that is positive!
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