ericjohnson
Newbie level 6
![Newbie level 6](/styles/images/ranks/blevel3.gif)
1.5bit/stage
Can someone please provide some good reference on how to design error correction circuit for 1.5b/stage pipelined ADC? If detailed circuit topology/schematic can be provided, that'll be greatly appreciated!
Can someone please provide some good reference on how to design error correction circuit for 1.5b/stage pipelined ADC? If detailed circuit topology/schematic can be provided, that'll be greatly appreciated!