bandgap ref not working properly

I recall in the 70's a former NSC analog guru by the name of R.A. Pease was the self-appointed Czar of bandgap references and all designers had to get their bandgap references approved thru him at National Semi before release in their IC's.

But this paper might help you.

You first need a startup circuit to put the core at a bias current
which allows it to operate as a poor man's op amp loop (pA
means gm is trivial and probably wrong). This is always fun,
getting robust startup across decades of leakage and VT
variation while never letting that current "bend" the PTAT.

I prefer a switched resistor that VBG coming up, turns off.
Some hysteresis here is good but may give DC OP /
sweeps a hard time.

The PTAT core is swung by your "vstack" and "vstack"
is the -outcome- (VBG) as well. The loop has to pick the
right answer and the outer loop (op amp) was deleted.

For this core to work as-is-ish one of the BJTs needs to
be connected C-B ("transdiode"). You can make the top
mirror simple (P : P w/ same W) or add a skosh of
cross-coupled gain there, must not allow this to become
hysteretic though.

Then you can push or pull startup current at one of the
diode-connected devices and see the "vstack" snap in and
the startup error current go away, leaving you with a reference.

Those presistors probably have a TC1=TC2=0, which is
wrong unless you're using metal thin film resistors (these
have close enough to 0 TC to make a bandgap difficult;
silicon resistors have a stronger tempco and that makes
a flat output TC (from PTAT active and NTAT passive
current-balance). But silicon resistors have a complex
(bowed) tempco which adds to error-band.

D.A.(Tony)Stewart said:

I recall in the 70's a former NSC analog guru by the name of R.A. Pease was the self-appointed Czar of bandgap references and all designers had to get their bandgap references approved thru him at National Semi before release in their IC's.

But this paper might help you.

http://ecad.tu-sofia.bg/et/1999/Statii%20ET99-I/Features%20and%20Limitations%20of%20CMOS%20Voltage%20References.pdf

Click to expand...

sorry, but i cant figure out what help that paper has for me. it had nothing regarding the problem I'm facing ig?

dick_freebird said:

You first need a startup circuit to put the core at a bias current
which allows it to operate as a poor man's op amp loop

Click to expand...

okay, so I need to add a start-up circuit to my bandgap right? let me just try that
I'm following a research paper that deals with designing a POR circuit that involves making a VDD threshold level detector block and a pulse generator. They followed this architecture, so I thought of trying out their way however the output of the first block that is the detector one isn't giving the correct results. Which has its bandgap core circuit as I posted above. Any insights into this would help. I am attaching the paper as well.

Paper link
F. Tabarani and H. Schumacher, "BiCMOS 7.5 µA power-on reset pulse generator circuit with precise threshold level and hysteresis," 2015 IEEE Bipolar/BiCMOS Circuits and Technology Meeting - BCTM, Boston, MA, USA, 2015, pp. 5-8, doi: 10.1109/BCTM.2015.7340551. keywords: {Pulse generation;Decision support systems;Photonic band gap;Threshold voltage;Detectors;Power demand;Logic gates;power-on reset (POR);pulse generator;start-up;low-power;brown-out detection;bandgap;accurate threshold},

Are your Nfet sources terminated to Vss? or 0V.

Why are you not getting any drain current? (35p 75p)

You must get Id when Vgs= Vgs(th) of at least 200nA without any NPN current.
Then rising Vb=Vstack > 300 mV will start to bias Ic currents towards drain threshold current where the gain in PSTAT and NSTAT rises quickly. If the emitter R's are too large then your gain is too low since the common emitter voltage gain is basically Rc/(Re+Rbe)

Here is a simulation where you can quickly thumb thru the 10% values to see the effects on node voltages and currents.

All FETs are identical and only the NPN's are intentionally mismatched with no thermal effects. Try to adjust Vbias and Re to match collector voltages. Now what is your drain voltage? If you set Id to 1uA or 10 uA. After you can adjust differential gain and offsets, you can match PTAT and NTAT more easily as you change the common mode gain with Vstack.

If your PTAT gain is too low and you get NTAT behaviour, then perhaps your emitter R values are too large compared to hFE * Rbe.

Examine your target currents and node voltages for sensitivity and balance.

For intuitive quick results, you can thumbwheel through all the 10% values in this simulation where all parts are perfectly matched except hFE's.

Now try to balance the collector voltages based on impedance ratios of collector /emitter to create a drain voltage such as 1.510. Compare with your circuit.

The Brokaw bandgap reference is based on a differential high gain of collector voltages to drive Vstack limited by the quadratic effects of Vbe and the linear effects of Re. Bias controls this gain. The correct R range affects the balance.

Vstack error requires a diff amp. R4 reduces Utemp for the best balance.


For more details and theory...

D.A.(Tony)Stewart said:

Are your Nfet sources terminated to Vss? or 0V.

Click to expand...

ah yes, i forgot to update the schematic that I uploaded.

it turns out that as soon as I added a start up circuit the output started to behave somewhat on the lines I wanted it to behave. Now increasing the PTAT contribution by increasing R3 (in the schematic) got the V_stack to curve more, but to get it to have a good BGR nature, I had to increase R3 to MegaOhms which seems absurd. Any thoughts on this?

Perhaps you should share your node voltages and spice file.zip for others to review in a readable format.