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[SOLVED] Force logic selection during synthesis

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keyboardcowboy

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Is it possible to tag some logic in a Verilog design and have design compiler implement it using a specific logic structure?. For example if I have combinational logic in a always(*) block and I want to have it synthesized using only NAND, NOR, and INVERTERS how can I do that?. Ordinarily it uses a cell which is a combination of NOR and OR gates
 

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keyboardcowboy said:
Is it possible to tag some logic in a Verilog design and have design compiler implement it using a specific logic structure?. For example if I have combinational logic in a always(*) block and I want to have it synthesized using only NAND, NOR, and INVERTERS how can I do that?. Ordinarily it uses a cell which is a combination of NOR and OR gates
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Not sure why on earth you’d WANT to do that, but in VHDL you can instantiate primitives. I assume you can do something similar in verilog, along with some KEEP directives. But, really, why?
 

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I know about logic primitives, but I want the synthesizer to use specific primitives (NAND, NOR, INV) for specific part of RTL. This is for some experiments I want to do
 

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set_target_library_subset
Restricts the optimization of a block to a subset of the target
libraries.

-use lib_cells
Specifies library cells that can be used for optimization within
the block. This is in addition to the libraries listed in the
library_file_name_list argument.

set_libcell_subset
Restricts the optimization of sequential cells and instantiated
combinational cells to a family of target libraries.
 
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In Cadence you use the set_dont_use command and you specify which gates it is allowed to use. If it is only in one block, you might have to tell it to set_dont_use, select the subcell, synthesize that only, set_dont_touch or set_size_only on it and then do the rest.
 
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