keyboardcowboy
Member level 3
![Member level 3](/styles/images/ranks/dlevel3.gif)
Consider a design below
UART read/write to the SRAM takes multiple cycle. Lets assume the minimum number is 7. What can be done if an AHB read/write request comes during those 7 cycles?. I am unable to find a mechanism in AHB that tells the CPU to not send a request while UART is reading/writing to the SRAM. Any ideas?
UART read/write to the SRAM takes multiple cycle. Lets assume the minimum number is 7. What can be done if an AHB read/write request comes during those 7 cycles?. I am unable to find a mechanism in AHB that tells the CPU to not send a request while UART is reading/writing to the SRAM. Any ideas?