keyboardcowboy
Member level 3
![Member level 3](/styles/images/ranks/dlevel3.gif)
Consider the following piece of Verilog
The pulse occurs during the negative period of clk_i but the simulator (Questasim) still shoes that it was captured by the flipflop. Why is that and does this also work after synthesis/in hardware?.
My understanding was that at the positive edge and before the next positive edge there was no pulse so flipflop should be 0 too, but that does not seem to be the case.
Code:
always @(posedge clk_i or negedge rst_n_i) begin
if(!rst_n_i) begin
flipflop <= 1'b0;
end else begin
if(pulse) begin
flipflop <= 1'b1;
end else begin
flipflop <= 1'b0;
end
end
end
The pulse occurs during the negative period of clk_i but the simulator (Questasim) still shoes that it was captured by the flipflop. Why is that and does this also work after synthesis/in hardware?.
My understanding was that at the positive edge and before the next positive edge there was no pulse so flipflop should be 0 too, but that does not seem to be the case.