Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

Ideas for high voltage level shifter/translator supporting negative voltage

E

ErenYeager97

Newbie level 6
Newbie level 6
Joined
May 12, 2024
Messages
11
Helped
0
Reputation
0
Reaction score
0
Trophy points
1
Visit site
Activity points
152
I have to design a level shifter that supports a positive swing signal (0 to 3.3V) and outputs a bidirectional swing signal (3.3V to -12V). What kind of level translator/shifter can be used here. From google search this kind of topology seems possible:

1716367021239.png


However, the voltage stress on typically 5V Vgs transistors will be an issue here
 
Sort by date Sort by votes
The schematic has logic gates (invert-gates). They output either hi or low. Or else it's a simplified schematic to convey an idea.

Is your signal the kind that requires analog response? A solution could be an ordinary op amp. You'll need a negative 12V supply rail in addition to your positive polarity rail.
 
Upvote 0 Downvote
,ou will have to defeat the Vgb limit on any plain JI flow.
Triple well or SOI can free the bodies to follow (subject
to limit-clamps and cascodes) the gate "enough to survive".
To the first (VDD-GND) stage add a second that works
from VDD-VNEG. Managing the terminal voltages device
by device is the necessary work.

If you have a high voltage device (both gate and drain)
this is much easier, though performance might be no
better than a cascode-stack of same voltage capability.
 
Upvote 0 Downvote
I would recommend working back-to-front, first get
an output stack which can switch clean rail to rail
without violating any terminal voltage pair limits on
any individual device. This may require you to go
through some rounds of technology vetting, device
selection and circuit design (especially if you are
forced into a low voltage flow that requires So4
"switches" to stand off the 15V (plus undeclared
tolerance and load / supply driven overshoots) -
single cascode is easy, double requires one active
gate-node driver with medium swing, triple is real messy -
this is why medium voltage power management
technologies exist).
 
Upvote 1 Downvote

LaTeX Commands Quick-Menu:

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top