how are the temperatures of, say, PVT and SS, FF, Typ corners are selected?

While selecting a worse corner SS for simulation (EMIR analysis), a question arose about what temperature to select in PVT worse corner case and how these two temperatures of Tj are not necessary the same , can anyone explain? I cannot explain why a PVT junction temp wouldn't also be the same as in SS.

these are the corners I've defined for our design requirements.

• Spice models, run with SS worse case:
  • SS ( worse case ): Low Vcc, high temp Tj @125C and, high threshold voltages.
  • FF ( Best case ): High Vcc, low temp Tj @ 0C, and low threshold voltages.
  • TT ( typical case ): Nom Vcc, nominal Tj @ 25C.

Electromigration is strongly accelerated by temperature so 125C.
The FF device corner may or may not be worse than the SS (leave
temperature and process distinct. Voltage is certain to increase
CVf current, so high.

Run a simple ring oscillator or something at 125C, max Vdd
and try all the process corners. Then you'll know (whether it's
accurate or not) what the PDK worst corner for interconnect
reliability is, by Idd.

dick_freebird said:

Electromigration is strongly accelerated by temperature so 125C.
The FF device corner may or may not be worse than the SS (leave
temperature and process distinct. Voltage is certain to increase
CVf current, so high.

Run a simple ring oscillator or something at 125C, max Vdd
and try all the process corners. Then you'll know (whether it's
accurate or not) what the PDK worst corner for interconnect
reliability is, by Idd.

Click to expand...

I have a PLL voltage-control oscillator and have run the SS corner; however, I have not simulated it using your suggestion @ 125c and max Vdd. Stay tuned and I will come back with the analysis.
I am still not sure how the junction temperature in the timing PVT was chosen? Tj chosen is ~10% less than process temp of 125C. but why would a designer choose this temp? the data sheet isn't telling me this.
What is the correlation between junction temp during a timing and EM simulation ? something easy to see like delay vs voltage.

It might have to do with temperature inversion and the notion that the fastest corner is not always the coldest temperature. perhaps the PDK is set up to give you freedom to combine models such that you make a call.

when in doubt, simulate all combinations. let the machines do the thinking

When performing PVT or process/production verification test plans, parameters are chosen to accelerate the weakest environment for voltage, temperature, noise ingress, vibration, thermal shock and it was common for me to choose a slew of tests to measure the margin to failure such as PLL lock range under such conditions or PSU no-load step overshoot or GBW or worst case slew rate. I would use this to determine BER test sensitivity on results for communications and HDD defects.

Since solderability for SMT was the highest risk in board production , the best way to prove-in a new process was to measure thermal profiles in the IR oven with 5g random vibration to a fixture holding the board during self test or some critical functional test. This could drop the yields quickly from 98% to 25% until the process was tuned for more robust solderability. Component failures were rare and a dozen solderability issues could be identified.

Whereas in ASIC's, stressors are clock & data, timing margins, race conditions or metastable so these are tested with matrix test vectors at worst cast and best case conditions for speed. Analog components parameters are tested for drift with statistical limits. Some of the best designs have loopback self tests with fault detection and isolation.

Not all defects are random so finding margins to failure is an important step which may be linear or not.