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How to decide ramp amplitude in PWM Buck converter

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nidare

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Hi

I am looking into a PWM buck design but having some struggles with understanding how to decide the ramp amplitude, reference voltage and modulator gain and their relation.

The modulator voltage gain is defined as Av_mod = Vin / Vramp

This I understand as the input voltage times the change in duty-cycle over the change in ramp voltage.

I have understood that it is important to make Vramp proportional to Vin by feedforward techniques to make Av_mod constant over input supply variations.

If rearranging the equation we end up with Vramp = Vin / Av_mod

My questions is then: what determines how to set the amplitude of Vramp?

I understand that it needs to be within the bounds of the input supply.

If having the flexibility of choosing the reference voltage to some degree, where should I place it and what relation does it have to Vramp? I have seen equations such as Vramp = VBG/DUC but I do not understand why it is true.

Since the amplitude of Vramp will influence the modulator gain, do I want to increase or decrease it? In the literature I have seen regarding type III compensation, it does not seem like modulator gain is taken into consideration when calculating the passives in the compensation. Won't it have an impact on the loop gain?
 
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Ramp amplitude will be set to get its timing clean across PVT.
At what voltage, across supply span and other influences, can
you achieve spec timing tolerance-across-all?

8V UVLO, 5V is probably good. 5V in, with 4V UVLO, you probably
end up with something like 2X VBG, a simple buffer-up.

The environment tends to determine low level block approaches,
then scale at (or closer to) the end for anything that bugs you.
 
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Thanks for your replies.

It seems like I am quite free in choosing Vramp and reference level as I realise that the error amp stage will figure out where to regulate relative to the ramp to produce the desired output voltage, given that it has enough gain to work with.

It also looks like having a larger ramp amplitude will offer more "resolution" for the error amplifier to work with but will require the output to have more swing.

"Likely you want the ramp amplitude to be slightly higher than the maximum output from the error amp, to avoid funny things happening otherwise.

Can you elaborate on this? I am thinking that if the error amp happens to swing above the ramp, this is caused by the buck not being able to supply the given load at 100% duty-cycle and output voltage will start to drop. This is unavoidable for this scenario?
 
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nidare said:
Can you elaborate on this? I am thinking that if the error amp happens to swing above the ramp
Click to expand...
I'm just saying that you need to know what happens when the error signal exceeds the ramp voltage.
It may just stay at 100% output duty-cycle, or may do something weird.
 
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crutschow said:
I'm just saying that you need to know what happens when the error signal exceeds the ramp voltage.
It may just stay at 100% output duty-cycle, or may do something weird.
Click to expand...
On occasion I have done basic PWM cores using a 1/3 - 2/3 VDD limit
pair and triangle wave, so that I could get true 0 - 100% duty (and a
first-order supply rejection, on frequency).

But allowing 100% duty in many cases is not a Good Thing, especially
if you're counting entirely on the inductor and on-time to control the
current.
 
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In single supply ramp generators;
1. When a Schmitt trigger relaxation osc is used for PWM the thresholds are typ. 1/3 to 2/3 so the PWM control goes between these reference voltages
2. When Vref has been defined in a regulator circuit, the ramp voltage is often 0 to Vref

From C. Basso's awesome textbook "Switch Mode Power Supplies"

1707571533019.png
 
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