snoop835
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Hi all,
I am currently need to understand the principle operation of fully differential switched capacitor comparator. The schematic and timing diagram are attached in pdf format.
let me quote the paragraph explaining the principle operation of the circuit.
'The sub-ADC in each pipeline stage consist of two fully diferential comparator shown in pdf attachment. In the 1.5 bit per stage architecture, the sub-ADC threshold are +Vref/4 and -Vref/4, where the ADC input range is -Vref to +Vref differential. The switched capacitor comparator operates on two phase non-overlapping clock. The differencing network samples Vref during phase Q2 onto capacitor C, while the input at capacitor 3C is shorted giving differential zero. During phase Q1, the input signal Vi is applied at the input of both capacitors, causing a differential voltage proportional to Vi - Vref/4 to appear at the
input of the comparator preamp. At the end of phase Q1 (Q1bar high) the regenerative
flip-flop is latched to make the comparison and produce digital levels at the
output Vo.During phase Q1, the input signal Vi is applied at the input of both capacitor
My problem is I don't fully understand the circuit operations. I want to understand the mathematics behind this operation. How to we get the threshold +vref/4 and
-Vref/4?
Pls help me on this.
thanks in advance
I am currently need to understand the principle operation of fully differential switched capacitor comparator. The schematic and timing diagram are attached in pdf format.
let me quote the paragraph explaining the principle operation of the circuit.
'The sub-ADC in each pipeline stage consist of two fully diferential comparator shown in pdf attachment. In the 1.5 bit per stage architecture, the sub-ADC threshold are +Vref/4 and -Vref/4, where the ADC input range is -Vref to +Vref differential. The switched capacitor comparator operates on two phase non-overlapping clock. The differencing network samples Vref during phase Q2 onto capacitor C, while the input at capacitor 3C is shorted giving differential zero. During phase Q1, the input signal Vi is applied at the input of both capacitors, causing a differential voltage proportional to Vi - Vref/4 to appear at the
input of the comparator preamp. At the end of phase Q1 (Q1bar high) the regenerative
flip-flop is latched to make the comparison and produce digital levels at the
output Vo.During phase Q1, the input signal Vi is applied at the input of both capacitor
My problem is I don't fully understand the circuit operations. I want to understand the mathematics behind this operation. How to we get the threshold +vref/4 and
-Vref/4?
Pls help me on this.
thanks in advance