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How to use Antenna diode

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Hi All,
I wanted to add antenna diode to the design of my analog IP which would be integrated to top level.
In pdk they have provided two antenna diodes for positive node and negative node protection:
n+ diff to pwell for positive node
p+ diff to nwell for negative node
Question 1:
How to decide if the charges accumulated during etching process on the node are positive or negative?
So in this case should I use both diode back to get protection for positive or negative charge?

Question 2:
As top level routing is unknown to me, how can I know gates of which devices are susceptible to antenna effect?

Question3:
How to size the antenna diode?

Any help here is appreciated :)
 

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it's not that the charge is negative or positive, the charge will aways want to go to ground. The device choice is if you are placing in an nwel or substrate.

The diode size is usually the default size, as small as possible.

Antenna errors can also be resolved without using diodes, the charge is an accumulation on the gate because of a long wire, normally on a lower metal such as met1/2 etc.
A simple solution is the connected the gate at a higher (highest) metal so that during fabrication the top metal is the last to connect to the gate, it only needs to be a short distance of a few microns .eg GATE POLY metal1>via1>met2>Via3>met3, upto high metal ie 5 for a few microns then back down to a lower metal such as met2 or met3, I can add a picture if I get time...
 

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k_90 said:
it's not that the charge is negative or positive, the charge will aways want to go to ground. The device choice is if you are placing in an nwel or substrate.

The diode size is usually the default size, as small as possible.

Antenna errors can also be resolved without using diodes, the charge is an accumulation on the gate because of a long wire, normally on a lower metal such as met1/2 etc.
A simple solution is the connected the gate at a higher (highest) metal so that during fabrication the top metal is the last to connect to the gate, it only needs to be a short distance of a few microns .eg GATE POLY metal1>via1>met2>Via3>met3, upto high metal ie 5 for a few microns then back down to a lower metal such as met2 or met3, I can add a picture if I get time...
Click to expand...
1679408687373.png



1679409216066.png



1679409243652.png
 
Last edited:

    andre_luis

    andre_luis

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You are trying to protect the gate oxide against its body.
In antenna-charging litho environments the S/D junctions
will "pull in" to the body they sit in. So make it about the
body (well).

For PMOS, ntap (P+ plug into NWell) makes a reverse
biased junction, which you want for anything that doesn't
have to swing its gate far into repletion. For NMOS, a ptap
(N+ plug intp Psub). I'd check those ptap, ntap namings
in the specific process docs, as you could go either way
in naming - what's the "plug", or what's it protecting?.
But the N+/P- or P+/N-, that's fundamental. And there's
almost certainly a page or two about it in one of the design
manuals that should come with the PDK.
 

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