predator89
Member level 1
Hi All,
I wanted to add antenna diode to the design of my analog IP which would be integrated to top level.
In pdk they have provided two antenna diodes for positive node and negative node protection:
n+ diff to pwell for positive node
p+ diff to nwell for negative node
Question 1:
How to decide if the charges accumulated during etching process on the node are positive or negative?
So in this case should I use both diode back to get protection for positive or negative charge?
Question 2:
As top level routing is unknown to me, how can I know gates of which devices are susceptible to antenna effect?
Question3:
How to size the antenna diode?
Any help here is appreciated
I wanted to add antenna diode to the design of my analog IP which would be integrated to top level.
In pdk they have provided two antenna diodes for positive node and negative node protection:
n+ diff to pwell for positive node
p+ diff to nwell for negative node
Question 1:
How to decide if the charges accumulated during etching process on the node are positive or negative?
So in this case should I use both diode back to get protection for positive or negative charge?
Question 2:
As top level routing is unknown to me, how can I know gates of which devices are susceptible to antenna effect?
Question3:
How to size the antenna diode?
Any help here is appreciated