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Positive edge-triggered flip flop does not work

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mohamis288

mohamis288

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I have implemented the Positive edge-triggered flip flop using the D-latch based diagram in cadence virtuoso.
For D-latch I have used the diagram in AckLP.png .
But it seems both edges are working.
What is the reason?

D-latch-based-positive-edge-triggered-D-flip-flop.png


AckLP.png
 

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mohamis288 said:
But it seems both edges are working. What is the reason?
Click to expand...
How fast are the edges (rise and fall times)?
They must be less than the circuit propagation delay.
 
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Solution
mohamis288 said:
About 300us or lower
Click to expand...
That's way too slow, and it causing your problem.
As I said, the rise/fall times need to be less than the circuit propagation delay, which is likely in the low ns region.
Use a Schmitt-trigger to reduce the signal transition times.
 

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Question what "implemented" means. A DFF made of
verilog gates that have no delay, will fail because the
"hang time" is -too short- (0) and the DFFs need the
phase lag as "transient memory", to work. I have seen
this while building "structural verilog" views from transistor
level cell libraries. Delay properties or delay elements
had to be added.

The same may be true with too-slow-changing inputs
using SPICE modeled transistors but the question is
fundamental.
 
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remove first inv from the diagram, and remove the inv from 2nd dff , and try

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