snoop835
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c-2c ladder
Hi all,
I want to design 8-bit C-2C Ladder Based DAC. The journal is attached for review.
From the journal (fig. 3), how do I implement the switches and what is the timing requirement for the switches? My thought is, for each of the capacitors, use 3 NMOS switches (one is connected to capacitor and vin with Gate connected to CLK1, the other switch is connected to capacitor and vref/2 with gate connected to the DAC's input bits, the last switch is connected to capacitor and gnd with gate connected to inverted DAC's input bits)
How do I decide the value for the capacitor? What's the reasonable value for the capacitors?
Anyone has a good reference in this topic?
Thanks in advance
Hi all,
I want to design 8-bit C-2C Ladder Based DAC. The journal is attached for review.
From the journal (fig. 3), how do I implement the switches and what is the timing requirement for the switches? My thought is, for each of the capacitors, use 3 NMOS switches (one is connected to capacitor and vin with Gate connected to CLK1, the other switch is connected to capacitor and vref/2 with gate connected to the DAC's input bits, the last switch is connected to capacitor and gnd with gate connected to inverted DAC's input bits)
How do I decide the value for the capacitor? What's the reasonable value for the capacitors?
Anyone has a good reference in this topic?
Thanks in advance