successive approximation register adc

any body knows how fast the 8bit SAR ADC using charge redistribution technology can reach? or the state of art

ablue

Hi,

I have read few journals and articles about resolution and speed of SAR ADC using charge redistribution. From my readings the highest sampling rate is about 10-40Ms/s. My thought is, to go for higher sampling rate use other topology such as flash or pipelined.

Are you currently designing one?

some paper said can run 10M~50M, but I think it can not be used in real apllication. I have designed 8~12 bit SAR ADC, if the sample rate is high, the DNL of charge based SAR ADC is bad.

Can you post those papers? I am curious to read the consumption at those speed!

SAR ADC's structure is more simple than that of pipeline and power dissipation may also be small compare with pipeline and flash.

the signal frequency is about 3MHz, and the spec is not very tough, so I think that SAR ADC may satisfy the requirment. Can you post those papers??

Thanks a lot

Here are some papers for your reference, hope it help ;-)

Hi ablue,

Could you tell me how do you decide the value of the capacitors for your charge redistribution DAC in your design? How do you implement the switches? Do you have any good reference on this?

thanks

Capacitor size mostly depend on KT/C noise and matching property of the process, for 8bit ADC matching usually is sufficient. the attenuation cap if you used may need some calibration.

Swtiches size should make sure to satisfy settling requirment.

I only read some papers that you posted^_^Thanks for your post papers anyway

Have you taped out some projects include SAR ADC?? And what is the spec of your design?

ablue

thank u all for your contributions,

i am interested in the same questions as snoop835.

however, i am new to the ADC buisness, my requirements are as follows :
10 bit, 4ksps, <1mW, die are around .12 mm², AMS .35µ.......in <5 months

i am confused between an SAR ADC and a ΣΔ, but i don't think i can deliver a ΣΔ in that short period, given the fact that this is my first converter project.

so i guess its the SAR ADC, but how do i go about realising it, books only provide the system level blocks that we all know, the papers where nice, but still how do i size the caps and how to implement the switch arrays and the SAR itself

many thanks

Added after 4 minutes:

here is a paper the grabed my attention,

i think it should be quick to implement but still i don't know how to implement the switching array.....

any ideas or references are much apprectiated.

many thanks

skyskysky said:

some paper said can run 10M~50M, but I think it can not be used in real apllication. I have designed 8~12 bit SAR ADC, if the sample rate is high, the DNL of charge based SAR ADC is bad.

Click to expand...

i m also designing a SAR adc please can you me me regarding this, I am designing successive approximation registers but am not able to design that please help me regarding this..

thankyou

Regards
Abhishek Mishra

I think most of your work will involve 10bit resolution comparator design,
After characterizing correctly, YOu have to work on offset voltage, and KT/C noise calcaulation, ( more assumption as a first cut).
Then you have to decide the RC delay from sample and Hold time period.
I think for 10bit resolution we can start with 100fF of capacitance ( see the transistor sizes of input stage of comparator).
Again, Ron resistance of switches have to be calibrated in the way, RC time constants are made equal for each capacitor array. And its 5RC <T/2, where T is the time period for clock.
YOu need to generate non overlapping clock, for clocked-latch comparator.

These are few inputs, Over the designing period many issues you may see and then you can work according to your will.
Anyway, I worked on 10MSPS ,10bit SAR ADC, with total power consumption was around 0.6mW. DNL was well below 0.5LSB.