VHDL: How do i read from file?

file inFile  : text open read_mode  is "input.txt";   -- input file
file outFile : text open write_mode is "output.txt";  -- output file

variable ln  : line;       -- string in file
variable ch  : character;  -- character in the line


readline(inFile,ln);       -- read string line from the file inFile and store it to "ln" 
read(ln,ch,res);           -- read next character "ch" from string line "ln"

write(ln,ch);              -- write character "ch" to line "ln"
writeline(outFile,ln);     -- write string to output file

library ieee,std;
use ieee.std_logic_1164.all;
use ieee.std_logic_textio.all;
use std.textio.all;

entity tb is
end tb;


architecture beh_tb of tb is

component dff
          port ( d : in bit;
          q : out bit;
          clk : in bit;
          rst : in bit
          );
end component;

signal d_s,q_s,clk_s,rst_s : bit;
signal cntr : bit ;

begin

U1 : dff port map ( d => d_s , q => q_s , clk => clk_s , rst => rst_s);

clk_gen : process
begin

    clk_s <= '0' ;
    wait for 5 ns;
    clk_s <= '1';
    wait for 5 ns;

end process;

reset_gen : process

begin

    rst_s <= '0' ;
    wait for 5 ns;
    rst_s <= '1' ;
    wait for 200 ns;

end process;

file_proc : process

file ipfile : text is in "/home/js17421/vhdl/text/ipf.txt";
file opfile : text is out "/home/js17421/vhdl/text/abc";

variable ip_line : line;
variable op_line : line;
variable d_v :bit;
variable i,j : integer;

begin

    while not(endfile(ipfile)) loop
      readline(ipfile,ip_line);
      read(ip_line,d_v);
      d_s <= d_v;
      i  := i + 1; 
      wait for 10 ns;

      assert not(endfile(ipfile))

      report " FILE FINISHED "
      severity note;

    end loop;

wait for 100 ns;

while (j < i) loop

    if (j = 1 ) then 
       write(op_line,string'("OUTPUT ") );
       writeline(opfile,op_line);
    end if;

    write(op_line,q_s);
    writeline(opfile,op_line);

    j := j + 1;
    wait for 10 ns;
end loop;

end process;


end beh_tb;