michaelScott
Junior Member level 2
Hello friends,
In my verilog code as you can see despite that i am able to see correct result in carrylookahead module, in the top module shows output as unknown value. What is the reason for that what coding i do wrong.
Thanks in advance.
In my verilog code as you can see despite that i am able to see correct result in carrylookahead module, in the top module shows output as unknown value. What is the reason for that what coding i do wrong.
Thanks in advance.
Code:
`timescale 1ns / 1ps
module alu(
input [31:0] X, //instruction input
input [31:0] A, //data input
input [31:0] B, //data input
output reg [31:0] C
);
wire [6:0] funct7;
assign funct7 = X[31:25];
wire [2:0] funct3;
assign funct3 = X[14:12];
wire [6:0] opcode;
assign opcode = X[6:0];
wire [11:0] imm;
assign imm = X[31:20];
wire [31:0] imm_i;
assign imm_i = {{20{imm[11]}}, imm[11:0]};
wire [31:0] mux_out;
mux_2x1 mux2x1(mux_out, B, imm_i, opcode[5]);
wire carry;
reg M;
wire [31:0] out;
carry_lookahead carry_lookahead_0(A, mux_out, M, out, carry);
always @(X, A, B)
begin
C = 0;
case (opcode)
7'b0110011: case(funct3)
3'b000: case(funct7[5])
1'b0: begin
M = 0;
C = out; //add
end
1'b1: begin
M = 1;
C = out; //sum
end
endcase
3'b001: C = A << B; //sll
3'b010: C = (A < B) ? 1'b1 : 1'b0; //slt(signed)
3'b011: C = (A < B) ? 1'b1 : 1'b0; //sltu(unsigned)
3'b100: C = A ^ B; //xor
3'b110: C = A | B; //or
3'b111: C = A & B; //and
endcase
7'b0010011: case(funct3)
3'b000: begin
M = 0;
C = out; //addi
end
3'b010: C = (A < imm_i) ? 1'b1 : 1'b0; //slti(signed)
3'b011: C = (A < imm_i) ? 1'b1 : 1'b0; //sltiu(signed)
3'b100: C = A ^ imm_i;//xori
3'b110: C = A | imm_i;//ori
3'b111: C = A & imm_i;//andi
endcase
endcase
end
endmodule