Layout routing using Poly

Hello,

It is very basic to know that poly has much resistance as compared to metal, hence when routing a current signal we should think about the voltage drop on the poly connector,
however, if routing a biasing voltage like the connection between the MOS gates, here there is ideally no current, hence no voltage drop problem,
so what will be the limitation of using the poly routing here?
I have a big matched transistor array in the length of 200 µm, and for no reason I am little afraid about connecting the gates using poly, that is why I switch to metal 1 at event segments of the array.

I am looking forward for your discussion

Best Regards

Poly routing is "prohibited" (weakly) because it "may" be an unmodeled design influence and then you have to check or waive other peoples' work beyond the "usual drill".

Represent poly routes as rpoly in layout and schematic and you have a story to sell, at least.

Large Rgg and fat FETs can make a current mirror that looks good for DC but adds Miller baggage on nodes that need to slew. A common HF PSRR "squirreliness" contributor.

Gate poly for nFET and pFET in an inverter are usually connected by the (field) poly.

Note that poly used in CMOS is typically "solicited poly", that acts more like a metal than as a poly.
A typical sheet resistivity for solicited gate poly is 10 Ohm/sq.

Funny, that "metal" gates used in more advanced technology nodes (~20nm and lower) have much higher effective sheet resistance than poly.

So, "metal" does not always mean "low resistance", and "metal gate" usually means "high resistance".

Silicided poly, usually selective (silicided by default unless sblock).
You may see rpolyh and rpolyl for unsilicided, silicided material
(or similar nomenclature). Field poly ought to be silicided. But run
at minimum groundrule width on modern nodes and it doesn't take
much distance to run up a 100-square "bar tab".... Gate dimension
has progressed faster than overall real estate compression, so the
squares count for a similarly built (say)

Sheet rho varies but should be disclosed in PDK docs. You can put
a "resistor/drawing" layer over routed poly and get an extracted
resistance (or most of it) in a kit that offers poly resistors. Then you
can inspect for consequences.

"however, if routing a biasing voltage like the connection between the MOS gates, here there is ideally no current"

It's wrong to think that there is no current in the gate network.
There is no DC current, but there is transient and AC current.
If you have too large gate resistance, it can bring in a lot of problems - slow response, slow switching, dynamic gate opening due to drain dV/dt effect (leading to shoot through current), etc.

Gate currents can be huge, several amps, in large and fast power FETs.
Construction of gate network, gate resistance, current flow uniformity, gate switching uniformity, etc. are very important effects, that should not be ignored.

Thank you friends for your answer

you have cleared this issue with me, specially the last answer from timof

hence, i will connect the gates of the transistors in the amplifier stage with much contacts as possible and switch it to metal one when possible.

for the current mirror of the biasing circuit i will use the poly since I dont care for the response or the switching performance

I would like to also to share with you guys this new and nice book about the layout design,



Thank you once again

Best Regards

Junus2012 said:

Thank you friends for your answer

you have cleared this issue with me, specially the last answer from timof

hence, i will connect the gates of the transistors in the amplifier stage with much contacts as possible and switch it to metal one when possible.

for the current mirror of the biasing circuit i will use the poly since I dont care for the response or the switching performance

I would like to also to share with you guys this new and nice book about the layout design,

Fundamentals of Layout Design for Electronic Circuits

This book provides the fundamental knowledge from technological constraints to reliability requirements necessary for a sound grounding from which to make practical use of the complete and indispensable application-oriented information regarding the physical design of electronic circuits.

link.springer.com

Thank you once again

Best Regards

Click to expand...

Well, for regular poly, you can put maximum one contact at each side, i.e. one or two contacts per one transistor instance.
The effective gate resistance (of one instance) for one-sided connected poly is 1/3*(W/L)*rsh, while for two-sided connected poly it's 1/12*(W/L)*rsh.
Here W is gate width (poly line length), L is gate length (poly line width), and rsh is poly sheet resistivity.
The factors 1/3 and 1/12 come from the distributed properties of the RC ladder of the gate network (and from a mathematically rigorous solution yielding hyperbolic functions).

If you want to reduce gate resistance, you do not put more contacts - instead, you split one finger into many, to get narrower gate width, connect all polys to M1 and up, and use metals to distribute the gate signal towards the poly contacts - to get low resistance, uniform delay distribution (over device area), etc.

timof said:

Well, for regular poly, you can put maximum one contact at each side, i.e. one or two contacts per one transistor instance.
The effective gate resistance (of one instance) for one-sided connected poly is 1/3*(W/L)*rsh, while for two-sided connected poly it's 1/12*(W/L)*rsh.
Here W is gate width (poly line length), L is gate length (poly line width), and rsh is poly sheet resistivity.
The factors 1/3 and 1/12 come from the distributed properties of the RC ladder of the gate network (and from a mathematically rigorous solution yielding hyperbolic functions).

If you want to reduce gate resistance, you do not put more contacts - instead, you split one finger into many, to get narrower gate width, connect all polys to M1 and up, and use metals to distribute the gate signal towards the poly contacts - to get low resistance, uniform delay distribution (over device area), etc.

Click to expand...

Thank you Tim for your nice explanation,
Here is the procedure I use as you also stated, I started to divide the transistor in multi-finger, then I connect all the fingers together using poly, then I evently distribute the via contact to M1 or M2, I can say that for every 8 segment gates I put one contact,
the biasing voltage will be routed by the this metal.

I have one question and it is important, what is the optimum channel width so I can say enough fingers, I have seen some people trying to avoide aspect ratio of greater than 10, so they divide until they reach, or there is other factors to decide?

Max distance to tap will be the final limiter for large devices.

dick_freebird said:

Max distance to tap will be the final limiter for large devices.

Click to expand...

thank you freebird for your reply,
I am sorry but couldn't understand your answer, could you please clear it for me

You often see a max-active-to-tap rule of 20u or some such.

That means the center of the centermost finger can't be more
than 20um from the inner edge of active*pplus (Nch) or
active*nplus (PMOS) tap / guardring. Given that there will
be some standoff of GR to S/D regions in the W-direction,
this means >= (40u-2*{tap-active} is the maximum DRC
driven width of a finger. Of course this specific rule will vary
w/ process (epi vs bulk vs SOI wafers, doping, how aggressive
the Ldrawn and LDDs / halo vs HCE...). Might be 5, might be
20u, I've even seen SOI with no body ties -allowed- (dumb
asses).

dick_freebird said:

You often see a max-active-to-tap rule of 20u or some such.

That means the center of the centermost finger can't be more
than 20um from the inner edge of active*pplus (Nch) or
active*nplus (PMOS) tap / guardring. Given that there will
be some standoff of GR to S/D regions in the W-direction,
this means >= (40u-2*{tap-active} is the maximum DRC
driven width of a finger. Of course this specific rule will vary
w/ process (epi vs bulk vs SOI wafers, doping, how aggressive
the Ldrawn and LDDs / halo vs HCE...). Might be 5, might be
20u, I've even seen SOI with no body ties -allowed- (dumb
asses).

Click to expand...

Thank you freebird for your answer, however my question was opposite to your answer, I am inquiring about the rule for maximum number if fingers I can go, what is the criteria where I should say it is enough to have 4 fingers as an example or having more,

I frequently read from some places that you divide your transistor to get preferable aspect ratio of 10 to 20, but cant understand why

you can see this argument from this nice document

I can't recall ever running into a max finger count limit that
was groundrule-driven.There may be other "soft limits" like
ugly aspect ratios (like, do you want 100 min-W fingers?)
at the high end, and the low "nf=" end is probably driven by
circuit performance or reliability concerns (current density,
source debiasing, gate resistance).

If you let the W go large then nf= will push on your tap-distance
and once nf*{S/D fingerL + gateL gets up around 20u you're back
to that.

dick_freebird said:

I can't recall ever running into a max finger count limit that
was groundrule-driven.There may be other "soft limits" like
ugly aspect ratios (like, do you want 100 min-W fingers?)
at the high end, and the low "nf=" end is probably driven by
circuit performance or reliability concerns (current density,
source debiasing, gate resistance).

If you let the W go large then nf= will push on your tap-distance
and once nf*{S/D fingerL + gateL gets up around 20u you're back
to that.

Click to expand...

Thank you freebird,
I would like to get more advantage from your experience

Suppose I have safe current density even with one finger and the gate resistance is fine for my circuit as well with one finger, however the transistor width is high, as you said looking ugly transistor, so do your try here to make it more square by increasing the number of gates, what is the preferable let me say the aspect ratio of this square and what have an advantage in the layout design.

my friend working just beside me has a transistors with W/L= 30µm/1µm, I advised him to reshape it but he continued to put it as it is, at the end with many other same size transistor his layout circuit is becoming square.

Thank you

That's smaller than a bond pad, by a lot, so it's not insane on
its face to have a single stripe. I would probably go with 2 or 4.
But that's not anything more than artist's choice, until you start
placing and packing neighbors and wires. Then you will see
other influences that don't pertain specifically to the device
in question - more about how it fits the surrounding "big
picture".

A single stripe can potentially deliver more current than a
pair, if the center stripe has to let current out the end and you
are unable / unwilling to explode and make-cell on a custom
layout. In either case you could fatten the S/D met1 by hand.
But a single stripe PCell, you could simply lay down a fatter
stripe.

Or take the current out vertically to fatter met2, and go from
there, with whatever base device layout you like for the
duty and the neighborhood.

Maybe I've spent too much time in custom analog, where
"anything goes, if you don't get caught" and there's not as
many rules to begin with.

Usually, multi-finger devices have an aspect ratio (ratio of the sides of the bounding box of poly) close to 1.
It may be 1.5, or 2.0, but not much more than that.
But there is no strict rule, and this may depend on other factors.
For example, if you make a power transistor, with a very low resistivity top metal layer, used of lateral current routing - then having a large aspect ratio multi-finger device may be beneficial - see an example of a power FET layout below, showing current distribution over the fingers, from my simulations.
Uniformity of current flow through multi-finger device is a very important characteristic.
Other important factor are:

- current flow uniformity through via and metals,
- avoidance of current density hot spots leading to EM violations,
- uniformity of current distribution through the ports / pads, etc.

You can run an analysis of Rdson, Rgate, and other characteristics, analyze the results, contributions from different nets, layers, and polygons, look at the distributions over the layout for hot spots or weak areas - and after a wile, you will get an experience and will know how to do this even without any analysis or simulation.

A while ago, I did a tutorial at ISPSD'2011 (International Symposium on Power Semiconductor Devices), on metal interconnects in power semiconductor devices, it showed layout best practices, physics, effects, simulation, pitfalls, optimizations etc.
I can try to find it.

timof said:

"however, if routing a biasing voltage like the connection between the MOS gates, here there is ideally no current"

It's wrong to think that there is no current in the gate network.
There is no DC current, but there is transient and AC current.
If you have too large gate resistance, it can bring in a lot of problems - slow response, slow switching, dynamic gate opening due to drain dV/dt effect (leading to shoot through current), etc.

Gate currents can be huge, several amps, in large and fast power FETs.
Construction of gate network, gate resistance, current flow uniformity, gate switching uniformity, etc. are very important effects, that should not be ignored.

Click to expand...

You are right. Also, there could also be gate leakage which is very likely not modelled. This will also lead to issues if your gate are is big.