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Adding example embedded designs to Vitis

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arminb73

arminb73

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Hello,
I am to use AXI UART16550 IP connected with ZYNQ7 PS to do some examples created by Xilinx in their software program Vitis: https://github.com/Xilinx/embeddedsw/tree/master/XilinxProcessorIPLib/drivers/uartns550
The main problem is I don't know how to add these examples to Vitis... The bitstream in Vivado has been created, and the platform project has also been created. All that is left is to add the code to Vitis.

unknown.png
 

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@arminb73
The main problem is I don't know how to add these examples to Vitis..
What do you mean by this?
Vitis is just a unified software from Xilinx which as several sub-parts.

Do you want to write the software targeted for the Zynq that will exercise the UART IP core?
 

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dpaul said:
@arminb73
The main problem is I don't know how to add these examples to Vitis..
What do you mean by this?
Vitis is just a unified software from Xilinx which as several sub-parts.

Do you want to write the software targeted for the Zynq that will exercise the UART IP core?
Click to expand...
Yes, that is what I am to accomplish.
 

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arminb73 said:
Yes, that is what I am to accomplish.
Click to expand...
Hello,

the first thing that you should to do is to check in your block design the memory map of your components in it - this values will be eksported to SDK (and then in software for PS). Vivado 2019.1 is the last wich have Xilinx SDK - the SDK is simpler to use comparing to Vitis. So maybe it is not stupid to make your block design in Vivado 2019.1 and then later write software in SDK. In the series of tutorials for wich I gave link it is exactly explain how to write software for block design in SDK. I\ didn;t use Vitis so far, but it looks similiar to SDK. Probably you should make "First Stage Bootloader" project for Zynq then load the bitstream an FSB to hardware (your FPGA board). The second stage is to make your software for PS (if there is "hello World" example just choose it. The first thing in software is initialization of PS, and then programing data exchange beetwen PL and PS. Writing software for PS is usually reading and writing proper values to used components registers - it is next to impossible to write it without study documentation.

Best regards
 
Last edited:

    arminb73

    arminb73

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FlyingDutch said:
Hello,

the first thing that you should to do is to check in your block design the memory map of your components in it - this values will be eksported to SDK (and then in software for PS). Vivado 2019.1 is the last wich have Xilinx SDK - the SDK is simpler to use comparing to Vitis. So maybe it is not stupid to make your block design in Vivado 2019.1 and then later write software in SDK. In the series of tutorials for wich I gave link it is exactly explain how to write software for block design in SDK. I\ didn;t use Vitis so far, but it looks similiar to SDK. Probably you should make "First Stage Bootloader" project for Zynq then load the bitstream an FSB to hardware (your FPGA board). The second stage is to make your software for PS (if there is "hello World" example just choose it. The first thing in software is initialization of PS, and then programing data exchange beetwen PL and PS. Writing software for PS is usually reading and writing proper values to used components registers - it is next to impossible to write it without study documentation.

Best regards
Click to expand...
You conclude by saying that writing software for PS involves reading and writing proper values to used component registers. I am fairly new to C, and I know that registers are found using their addresses, but I'm not sure how to get to this register, and if I do, what can I achieve by changing some bits in it? Having trouble understanding the different capabilities of IPs, such as AXI UART16550

1637939629530.png


Best regards
 

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arminb73 said:
You conclude by saying that writing software for PS involves reading and writing proper values to used component registers. I am fairly new to C, and I know that registers are found using their addresses, but I'm not sure how to get to this register, and if I do, what can I achieve by changing some bits in it? Having trouble understanding the different capabilities of IPs, such as AXI UART16550

...
Click to expand...
Hello,

it isn't easy (especially for newbie). On this WWW page you can find example of implementation In C language for this IP Core:

https://xilinx-wiki.atlassian.net/wiki/spaces/A/pages/18842080/AXI+UART+16550+standalone+driver

Here is example source code in Xilinx Github:

https://github.com/Xilinx/embeddedsw/tree/master/XilinxProcessorIPLib/drivers/uartns550/examples

In this file (header file) you can find important UART hardware parameters :

https://github.com/Xilinx/embeddeds...essorIPLib/drivers/uartns550/src/xuartns550.h

Best regards
--- Updated ---

hello,

I think that in your case it is a good idea ot watch this series of video tutorials (many thing will be clear after watching them):


Best regards
 
Last edited:
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dpaul said:
@arminb73
The main problem is I don't know how to add these examples to Vitis..
What do you mean by this?
Vitis is just a unified software from Xilinx which as several sub-parts.

Do you want to write the software targeted for the Zynq that will exercise the UART IP core?
Click to expand...
Good day, dpaul. Yes, that is what I want to be able to achieve.
 

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@arminb73
Did you study the tutorials mentioned above FlyingDutch?
Did you understand them?
Do you have a specific problem?
 

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