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Synopsys PrimeTime/TestMax and Xilinx Vivado

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gengarchitect

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Hello everyone!
I am a new student and recently got into timing fault analysis. I use Xilinx Vivado to compile the bitstream and upload it to my FPGA (PYNQ-Z1). Now I want to analyze the little program I programmed in Verilog. I found out that to analyze timing faults in TestMax, I will need to use PrimeTime. Now the problem for me is, I am not sure how to get the .db files for PrimeTime. Whenever I see a PrimeTime workflow, it says I need to link my design to a .db file. But I am unsure how to get those files.

Any advice and help is appreciated.
Thank you!
 

AFAIK, Vivado doesn't output .db files. Vivado also does it's own timing analysis during and after place and route.

Not exactly sure why you are trying to use ASIC tools on an FPGA.
 

Which tools give me .db output files? Can I input my verilog files into a program that gives me .db files? I programmed an ALU and I just want to check how TestMax outputs all the possible patterns for a timing fault analysis. I am just using FPGA because I am getting into chip programming and with an FPGA I can always reprogram it.

Thank you for your time!
 

fault analysis is an ASIC task, it has nothing to do with FPGAs. You are mixing two flows, that's why you don't know what a .db file is or how to use it.
 

fault analysis is an ASIC task, it has nothing to do with FPGAs. You are mixing two flows, that's why you don't know what a .db file is or how to use it.
Why is fault analysis an ASIC exclusive task? I thought you could do fault analysis on any hardware implementation. I am very sorry for asking obvious questions. Can you please elaborate what a .db file actually is and how to get one? I appreciate your help!
 

FPGA boards are tested for defects at fabrication time. Someone already took care of the fault analysis for you.

a .db file contains characterization information about standard cells in a library. all delays and power values are there. you get one from the library provider.
 
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