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Error with using BUFGCE in vivado 2019 (in "place_design" step)

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MSAKARIM

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I used around 16 BUFGCE in my design as a clock buffer, it passes in the synthesis step, but it gives me this error in "place_design" step:

[Place 30-120] Sub-optimal placement for a BUFG-BUFG cascade pair. If this sub optimal condition is acceptable for this design, you may use the CLOCK_DEDICATED_ROUTE constraint in the .xdc file to demote this message to a WARNING. However, the use of this override is highly discouraged. These examples can be used directly in the .xdc file to override this clock rule.
< set_property CLOCK_DEDICATED_ROUTE ANY_CMT_COLUMN [get_nets clk1] >

BUFGCE_inst_1 (BUFGCTRL.O) is provisionally placed by clockplacer on BUFGCTRL_X0Y0
IP_1/BUFGCE_inst_0 (BUFGCTRL.I0) is provisionally placed by clockplacer on BUFGCTRL_X0Y1
IP_2/BUFGCE_inst_1 (BUFGCTRL.I0) is provisionally placed by clockplacer on BUFGCTRL_X0Y2
IP_3/BUFGCE_inst_4 (BUFGCTRL.I0) is provisionally placed by clockplacer on BUFGCTRL_X0Y5
IP_4/BUFGCE_inst_2 (BUFGCTRL.I0) is provisionally placed by clockplacer on BUFGCTRL_X0Y3
IP_5/BUFGCE_inst_3 (BUFGCTRL.I0) is provisionally placed by clockplacer on BUFGCTRL_X0Y4
IP_6/BUFGCE_inst_6 (BUFGCTRL.I0) is provisionally placed by clockplacer on BUFGCTRL_X0Y7
IP_7/BUFGCE_inst_5 (BUFGCTRL.I0) is provisionally placed by clockplacer on BUFGCTRL_X0Y6
IP_8/BUFGCE_inst_B (BUFGCTRL.I0) is provisionally placed by clockplacer on BUFGCTRL_X0Y12
IP_9/BUFGCE_inst_C (BUFGCTRL.I0) is provisionally placed by clockplacer on BUFGCTRL_X0Y13
IP_10/BUFGCE_inst_9 (BUFGCTRL.I0) is provisionally placed by clockplacer on BUFGCTRL_X0Y10
IP_11/BUFGCE_inst_8 (BUFGCTRL.I0) is provisionally placed by clockplacer on BUFGCTRL_X0Y9
IP_12/BUFGCE_inst_7 (BUFGCTRL.I0) is provisionally placed by clockplacer on BUFGCTRL_X0Y8
IP_13/BUFGCE_inst_A (BUFGCTRL.I0) is provisionally placed by clockplacer on BUFGCTRL_X0Y11
IP_14/BUFGCE_inst_D (BUFGCTRL.I0) is provisionally placed by clockplacer on BUFGCTRL_X0Y14
Sig1/BUFGCE_inst_sig1 (BUFGCTRL.I0) is provisionally placed by clockplacer on BUFGCTRL_X0Y16
Sig2/BUFGCE_inst_sig2 (BUFGCTRL.I0) is provisionally placed by clockplacer on BUFGCTRL_X0Y15
Sig3/BUFGCE_inst_sig3 (BUFGCTRL.I0) is provisionally placed by clockplacer on BUFGCTRL_X0Y17

The above error could possibly be related to other connected instances. Following is a list of
all the related clock rules and their respective instances.

Clock Rule: rule_gclkio_bufg
Status: PASS
Rule Description: An IOB driving a BUFG must use a CCIO in the same half side (top/bottom) of chip
as the BUFG
clk_IBUF_inst (IBUF.O) is provisionally placed by clockplacer on IOB_X0Y78
and BUFGCE_inst_1 (BUFGCTRL.I0) is provisionally placed by clockplacer on BUFGCTRL_X0Y0
 

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Just a guess, but you might be trying to put the buffer on signals that can’t have that kind of buffer, so the tool is adding another buffer in front of it. Then the PAR is unhappy with two buffers .
 

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    MSAKARIM

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you could just let the tool place buffers. In other words, don’t instantiate any buffers in your code. This might be all you need.

you don’t say anything about the complexity or speed of your design, or even why you WANT a BUFGCE to begin with.
 
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@MSAKARIM ,
Barry is correct.
In an FPGA based design (I can speak for Xilinx and Microsemi) you do not manually instantiate the BUFG for your clock path/s (or any signal that needs to reach most parts of the design). Let the tool will do it for you.
 
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barry said:
you could just let the tool place buffers. In other words, don’t instantiate any buffers in your code. This might be all you need.

you don’t say anything about the complexity or speed of your design, or even why you WANT a BUFGCE to begin with.
Click to expand...
I need the function of clock gating in my design (for some circuits that are idle for a while of time to save some of the dynamic power). So, after searching I found that BUFGCE is the best clock-enable circuit for FPGAs.
--- Updated ---

dpaul said:
@MSAKARIM ,
Barry is correct.
In an FPGA based design (I can speak for Xilinx and Microsemi) you do not manually instantiate the BUFG for your clock path/s (or any signal that needs to reach most parts of the design). Let the tool will do it for you.
Click to expand...
I need the function of clock gating in my design (for some circuits that are idle for a while of time to save some of the dynamic power). So, after searching I found that BUFGCE is the best clock enable circuits for FPGA
 

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Hi,

some weeks ago there was a discussion about clock gating and supply current.
I recommended to do some measurements
* with true clock gating
* and with continous clock, but disbaled gates (inactive ENABLE of gates)

To find out the true power saving benefits. I guess we didn´t see a result (sadly).

The second one should be the standard way to disbale functions and thus save power/energy/disspated heat.

It would be great if you could give some information about current consumption of both cases.
It will also help many people in future.

Klaus
 

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@MSAKARIM ,
Yes BUFGCE needs to be used for clock gating.

But do you really need 16x BUFGCEs? i.e. do you have 16 different main clocks in your design?
How many PLLs/MMCMs does your design have?
Can you not use fewer BUFGCEs and switch off the clock/s at a higher level?

Well in order to answer your question better regarding the use and placement of BUFGCEs we need to understand your clocking architecture.
 

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If your design really was so power critical that you need clock gating to disable a clock, You liklely wouldnt be using an FPGA. You'll probably find that disabling the clock wont really give much of a power saving. You'd be better off (and much easier for you) to simply use clock enables.
 

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Clock gating is used in ASICs; I don't think it's advisable, or, as others have pointed out, even useful in an FPGA.

Further, using clock enables might save you just as much power, without the problems of gated clocks.
 

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