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Triggering clock pulse between scan shift is usually appeared in capture cycle. In which the injected test pattern has been applied to internal combo. logic. An extra clock pulse (capture clock) is used to latch the internal combo. output to scan FF and then shift out for measurement.
In order to test the manufactured design, the scan-chain method is often used.
Because the objective of scan-chain circuits is mainly to test the combinational logic between Flip Flops, the necessities to scan the stimuli to the inputs of the combinationa logic is required; however since the utility of scan-chain methods is to reduce the number of pins of the chip; therefore the serial method is always taken so that the scan clock should be utilized to transfer the serial stimuli into the parallel ones. Even if not, in order to test the large number of cones between the Flip flops, we can only test one of the cones at a time so that a scan clock is needed. Currently, there are two ways to test the function of the combinational logics: internal testing logic such as BSIT and external devices such as ATE which often is expensive and less tesing pins than the pins on the chip.
basic scan sequence:
1) Apply data to primary input (PI)
2) Shifting in scan vector into scan chains through scan in (SI) pins.
3) Scan capture. In this state, scan enable pin is set to low.
4) Shifting out - measure primary output (PO) and Scan out (SO) pins
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