beetwee
Junior Member level 3
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I have a circuit with a large PMOS area consisting of current mirrors. Between the PMOS gate and VDD, there is a big capacitor, based on a pmos in pwell varactor (DNW underneath, pwell biased to vdd). Hence, the well of the PMOS and the capacitors are all biased to VDD.
When I run Calibre xRC, there is a lot of intrinsic cap ("C") to the specified ground node, as well as CC caps to the specified ground node. However, I expected that this should be referred to VDD, as the local substrate is all Nwell biased to VDD.
Trying to understand this, I made a simple testcase and found out that for calibre xRC, it doens't matter wheter I put nwell (biased to vdd) or not under a metal strip. The capacitance is always referenced to the ground node.
How can I solve this, as I cannot trust the AC results when parasitic cap in the PMOS area is grounded?
After reading the manual, I have disabled the options: ground all coupling capacitors and use the setting: extract floating nets: all.
When I run Calibre xRC, there is a lot of intrinsic cap ("C") to the specified ground node, as well as CC caps to the specified ground node. However, I expected that this should be referred to VDD, as the local substrate is all Nwell biased to VDD.
Trying to understand this, I made a simple testcase and found out that for calibre xRC, it doens't matter wheter I put nwell (biased to vdd) or not under a metal strip. The capacitance is always referenced to the ground node.
How can I solve this, as I cannot trust the AC results when parasitic cap in the PMOS area is grounded?
After reading the manual, I have disabled the options: ground all coupling capacitors and use the setting: extract floating nets: all.