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SystemVerilog syntax code help

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hcu

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Hi,

I have a doubt about the SystemVerilog code snippet.

Code: 
    sub_top #(
    ) inst_sub_top (
    .count((VALUE[FACTOR-1:0] - {{(FACTOR-1){1'b0}},1'b1})),
    .dummy()
    );

where VALUE is a parameter defined as 4, while FACTOR is a local param which is a 2.
How to understand this line
((VALUE[FACTOR-1:0] - {{(FACTOR-1){1'b0}},1'b1})) . Note: No syntax errors.
 

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Not sure how this is supposed to work with the given VALUE = 4 and FACTOR = 2 as the result ends up being -1.

((VALUE[FACTOR-1:0] - {{(FACTOR-1){1'b0}},1'b1}))

VALUE[2-1:0] = VALUE[1:0]

FACTOR-1 = 2-1 = 1
{ {1{1'b0}}, 1'b1}, where {x,y} is concatenation of x and y

The 1 in {1{x}} is the repeat value. e.g. {3{1'b0}} = 3'b000
in this case it is 1'b0

so the line means.
.count (VALUE[1:0] - 2'b01),
 

    H

    hcu

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