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IMPACT : Can't open /dev/parport0: No such file or directory

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I tried the following setting, but the error still persists.

9V0edkf.png
 

Thanks @niciki for that valuable advice

For those looking for similar solution, remember also clean up the tmp folder under ipcore_dir folder before regenerating the core using version 1.04.a
--- Updated ---

However, when I try to choose different setting within the VIO CORE, I encountered the same error again. Why ?

XZ63ff1.png
 
Last edited:

The tool tries to generate example_design which contains further subfolders.

Maybe the path to the project is simply too long?
 

Removing the "Generate Example Design" option eliminated the error. Not entirely sure why.
--- Updated ---

Now that it seems that I have the necessary files generated for chipscope. However, the design hierarchy still does not show anything related to chipscope.

In other words, how do I instantiate or initiate the use of the generated chipscope core inside ISE Project Navigator ?

MpfhImb.png
 

Instantiate ICON and VIO in your HDL. Connect clocks to ICON/VIO and your signals to VIO. Then you will see that generated cores will be in the ISE project tree.
 

@niciki I only have this verilog wrapper file inside ipcore_dir folder ?

Code: 
///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 2021 Xilinx, Inc.
// All Rights Reserved
///////////////////////////////////////////////////////////////////////////////
//   ____  ____
//  /   /\/   /
// /___/  \  /    Vendor     : Xilinx
// \   \   \/     Version    : 14.7
//  \   \         Application: Xilinx CORE Generator
//  /   /         Filename   : chipscope_vio.v
// /___/   /\     Timestamp  : Wed Apr 28 15:34:04 +08 2021
// \   \  /  \
//  \___\/\___\
//
// Design Name: Verilog Synthesis Wrapper
///////////////////////////////////////////////////////////////////////////////
// This wrapper is used to integrate with Project Navigator and PlanAhead

`timescale 1ns/1ps

module chipscope_vio(
    CONTROL,
    CLK,
    ASYNC_IN,
    ASYNC_OUT,
    SYNC_IN,
    SYNC_OUT) /* synthesis syn_black_box syn_noprune=1 */;


inout [35 : 0] CONTROL;
input CLK;
input [15 : 0] ASYNC_IN;
output [15 : 0] ASYNC_OUT;
input [15 : 0] SYNC_IN;
output [15 : 0] SYNC_OUT;

endmodule
 

The answer is in the datasheet of the ip core. The problem with not generating VIO core was weird and interesting, but now you have a fairly basic question that you will find answer in the spec.
 

promach said:
it seems that VIO core could only capture maximum 4 signals ?
Click to expand...
From what source you get that statement?

From DS284 June 22, 2011:
1. A maximum of 15 VIO cores can be used in a single design.
2. You can specify a port width up to 256 bits for Async Input/Async Output/Sync Input/Sync Output for each VIO core.

promach said:
and ILA core could only capture 1 signal with multiple triggers ?
Click to expand...
ug750 tells that ILA core can only capture 1 signal with multiple triggers? Where?

From DS299 June 22, 2011:
1. There are a maximum of 16 trigger ports on each ILA. Each trigger port can consist of between 1 and 256 signals.
2. When the Data Same as Trigger check box is selected: • The data and trigger ports are identical.
3. When the Data Same as Trigger check box is not selected • The data port is completely independent of the trigger ports.

IMO it seams that you don't read needed datasheets to understand chipscope. Nobody will read it by you and I feel that I am wasting me time to assist and answering to your basic questions.
BTW: This thread "IMPACT : Can't open /dev/parport0: No such file or directory" right now is regarding chipscope and not IMPACT. I suggest to start a new thread.
 

promach said:
it seems that VIO core could only capture maximum 4 signals ?

and ILA core could only capture 1 signal with multiple triggers ?
Click to expand...
Besides what niciki has said, why are you pointing to a document that describes how to use the ILA inserter, you are instantiating the ILA and ICON?

There are two methods to add a ILA to debug your design in ISE. One method is generating the IP cores and instantiating them in your design (the method you've been asking about). The other method is to use the ILA inserter, which is what the above document being referenced describes. IIRC you have at least synthesize the design and then launch the inserter and set the number of triggers, and select the signals and the clock. The inserter then generates the appropriate cores and inserts them into the desgin (without having to modify your design files). The only issue with this method is you may have trouble finding your signals if the synthesis optimized them.
 

    P

    promach

    Points: 2
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