Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

Small signal S-parameter measurements of RF power amplifier using VNA

Status
Not open for further replies.
Georgy.Moshkin said:
Biasing lines do not look good. If those are 50 Ohm SMA connectors, microstrip looks too thin. Probably it is better to put input and output biasing farther away. I really would recommend to order some generic FR4 1.0mm boards manufactured at PCB fab based on your layout, with nice vias and everything, and you can put several prototypes on a single board, and obtain good results much easier. You can even put some resonator and estimate dielectric constant. I do not see what transistor do you use. I only familiar with low power FETs, many of them usually are stable if terminated with 50 Ohm (unstable circle boundaries are very far from center) and source pin is grounded very well with VIAS on a relatively thin substrate, for example 1.0mm or thinner FR4. Same transistors oscillate easily if termination is far from 50 Ohm, or there is bad grounding, when substrate is too thick and/or vias are too far from source pins, unstable circles are quickly "moved" to the center of Smith chart.
I would use radial quarter wave stubs for biasing, use thinnest possible biasing lines. On FR4 with Er=4.5 H=1.0mm main 50Ohm line width is 1.85mm. Biasing line may be around 0.3mm thick, quarterwave length between 50Ohm line and radial stub will be 18mm.
The only problem would left is finding good capacitors for DC blocking, or using special ones which are pretty expensive.

Possible design:
1) 4x4cm ground area around transistor on top layer, with many vias around source pins. Input and output lines are GCPW lines.
2) rounded transition from GCPW to microstrip on the edges of 4x4cm ground area. Both for input and output.
3) 0.2 mm thin biasing lines with radial stubs.
4) commercial DC block capacitors somewhere near SMA connectors.
On a FR4 substrate at 2.4GHz it will perform pretty the same even if Er will be 3.5 or 5.5, with or without solder mask, with high or low dielectric losses. Phase length and characteristic impedance do not change much at 2.4GHz. You probably will get more differences from how SMA connectors and transistor was soldered. If every component is ok and layout arrangement is good, and you checked stability circles, then there will be no impedance "swirling" around Smith chart through unstable regions of transistor as dielectric constant changes or if you connect SMA cables with different length or something like that.
Large copper area around transistor will help to dissipate more heat, putting thin biasing lines away from transistor gives lower temperature and higher possible currents (https://www.eeweb.com/tools/external-pcb-trace-max-current/), minimizes input to output coupling and forming of unwanted parallel feedback oscillator.
Click to expand...
The used substrate is roger 5880 with Er = 2.20 and h= 0.79 mm. So based on these values, the width of 50 ohm biasing line is 2.5 mm. The transistor used is CGH40010F high power transistor (10 watt) provided by cree company (place on the middle of the board). This type of transistors is designed to be mounted directly on the heatsink for source ground connection. For DC blocking, I use the commercial one from keysight technology (Agilent 11742A blocking capacitor). I do not understand "put biasing further away"? As the biasing line are 50 ohm quarter-wavelength connected at the gate and drain terminals of the transistor.
 

-Your layout looks weird.A Wide Microstrip Line then a very Narrow MS Line..It's unusual Impedance Matching.Have you ever simulated your layout in Momentum or similar EM Simulator ?I believe there are many errors in Design.
-If the PCB is Double Sided ( Bottom Side is completely GND ), connection method of Decoupling Capacitors is completely wrong.A single screw cannot provide a good GND connection.There must be many VIAs connected to Bottom Side ( GND )
-Decoupling Capacitors cannot be soldered as you wish.First small valued Capacitors then bigger valued ones.( find why ?)
-Connectors are also bad mounted.There have to be many VIAs around GND Connection of the Connectors so both side should be connected very well together
-Research and Inspire from similar PCBs of different Manufacturers.
1606719222314.png
 
Last edited:

    M

    Mabrok

    Points: 2
    Helpful Answer Positive Rating
BigBoss said:
-Your layout looks weird.A Wide Microstrip Line then a very Narrow MS Line..It's unusual Impedance Matching.Have you ever simulated your layout in Momentum or similar EM Simulator ?I believe there are many errors in Design.
-If the PCB is Double Sided ( Bottom Side is completely GND ), connection method of Decoupling Capacitors is completely wrong.A single screw cannot provide a good GND connection.There must be many VIAs connected to Bottom Side ( GND )
-Decoupling Capacitors cannot be soldered as you wish.First small valued Capacitors then bigger valued ones.( find why ?)
-Connectors are also bad mounted.There have to be many VIAs around GND Connection of the Connectors so both side should be connected very well together
-Research and Inspire from similar PCBs of different Manufacturers.View attachment 165979
Click to expand...
Yes I have simulated the design using EM-Co-simulation ADS (I have simualted the layout first (without components) using momentum simulation, then created symbol. Lastly, I opened that symbol in schematic window and connected the components and simulated. The results was as expected.
 

If simulation and prototype layout are totally the same, there are several potential problems:
1. Most likely grounding in your prototype differs from simulation.
2. What is characteristic impedance of wide and thin line? Probably need to check all characteristic impedances one more time. SMA connector line looks more like a 100 Ohm line.
3. Maybe you did not looked into stability much? I remember there is a stability circle component in ADS, it may be used in S-parameter simulation. You may try to put such component on both input and output of transistor, then draw input and output stability circles. Your input and output matching networks transform 50 Ohm to some other (complex) impedance, and you can check if those impedances are out of unstable regions with a good margin. And if this margin is very small, then oscillations may still start at some point.
 
Last edited:

What is your opinion about the harmonic termination in the output matching network? As during my design process i only considered the fundamental matching and Ignore the harmonics?
 

I think S-parameters must be checked first. It may be *.s2p file from manufacturer or you can obtain S-parameters in ADS: apply required voltages through biasing network (without matching network), connect input and output to Port1 and Port2 through DC block component, then perform S-parameter simulation from few MHz to 5GHz. For amplifier stability is probably most important part.
 

    M

    Mabrok

    Points: 2
    Helpful Answer Positive Rating
Georgy.Moshkin said:
I think S-parameters must be checked first. It may be *.s2p file from manufacturer or you can obtain S-parameters in ADS: apply required voltages through biasing network (without matching network), connect input and output to Port1 and Port2 through DC block component, then perform S-parameter simulation from few MHz to 5GHz. For amplifier stability is probably most important part.
Click to expand...
I have large signal model of the transistor provided by the manufacturer
 

I do not have any experience working with large signal data. I may be wrong, but if it is nonlinear model, then without applying input signal you can measure small signal S-parameters using simulation, very similar to Figure 1-1 in https://literature.cdn.keysight.com/litweb/pdf/ads2004a/pdf/cktsimlssp.pdf
but without LSSP component. This file looks interesting too: https://vtechworks.lib.vt.edu/bitstream/handle/10919/11116/chap4.PDF - for general arrangements of the ADS probe components.
In other words, you can get some clues on why your prototype is unstable by looking at S-parameters in simulation. Just apply the same biasing, but do not add any matching networks. We need bare-bone S-parameters on transistor outputs when connected to 50 Ohm ports through DC blocks. After obtaining S-parameters from simulation you porbably can put your matching networks on the same sheet in ADS, or there was some kind of component to measure S-parameters looking into transistor and into matching network at the same time, I do not exactly how I did it. For some reason I used simple port termination from. Port1 and Port2 for transistor. Port3 and Port4 for input matching network. Port5 and Port6 for output matching network. And using that setup I was able to draw stability circles, and impedance points of input and output matching network relative to those circles. It gave me very good understanding on why my amplifier oscillated, for example changing substrate height from 1.6mm to 1.0mm made transistor stable because source pin reduced length (and inductance), and on Smith chart this tiny 0.4mm change moved unstable region very far away from the center. In my opinion the best way is to work with stability circles, or at least plot a k-factor.
 
Last edited:

    M

    Mabrok

    Points: 2
    Helpful Answer Positive Rating
Georgy.Moshkin said:
I do not have any experience working with large signal data. I may be wrong, but if it is nonlinear model, then without applying input signal you can measure small signal S-parameters using simulation, very similar to Figure 1-1 in https://literature.cdn.keysight.com/litweb/pdf/ads2004a/pdf/cktsimlssp.pdf
but without LSSP component. This file looks interesting too: https://vtechworks.lib.vt.edu/bitstream/handle/10919/11116/chap4.PDF - for general arrangements of the ADS probe components.
In other words, you can get some clues on why your prototype is unstable by looking at S-parameters in simulation. Just apply the same biasing, but do not add any matching networks. We need bare-bone S-parameters on transistor outputs when connected to 50 Ohm ports through DC blocks. After obtaining S-parameters from simulation you porbably can put your matching networks on the same sheet in ADS, or there was some kind of component to measure S-parameters looking into transistor and into matching network at the same time, I do not exactly how I did it. For some reason I used simple port termination from. Port1 and Port2 for transistor. Port3 and Port4 for input matching network. Port5 and Port6 for output matching network. And using that setup I was able to draw stability circles, and impedance points of input and output matching network relative to those circles. It gave me very good understanding on why my amplifier oscillated, for example changing substrate height from 1.6mm to 1.0mm made transistor stable because source pin reduced length (and inductance), and on Smith chart this tiny 0.4mm change moved unstable region very far away from the center. In my opinion the best way is to work with stability circles, or at least plot a k-factor.
Click to expand...
Based in your experience, how much the stability factor K (minimum value) should be? Theoretically I know that it should be K>1, but I need to know based in your experience the margin between simulation and measurements?
For example if the K= 1.2 during the simulation, will be stable during the measurements?
 

I would try to maximize K while other parameters do not degrade too much, for example gain. K= 1.2 may be good if your simulation is closely resembles real prototype. But I would not be surprised if it oscillates. Component parameters may be loose, simulation and model may be not perfect either. Did you tried to run transient simulation? If you are learning maybe it is time to consult with your professor. If you are doing commercial product, you probably need to dig deeper into oscillation cause, and read something on classical design steps for large signal amplification in ADS. In my understanding for small signal transistors applying signals only can "rotate" and scale a little bit the whole set of S-parameters without any significant changes. So my approach was always to look at stability circles and then check how stable it will remain if i scale and rotate terminating impedances a little bit.

A little unrelated information: Instead of k-factor I used formulas for stability circle center and radius. For example. D=sqrt( (x2-x1)^2+(y2-y1)^2)-R, D - distance between outer of unstable circle to termination impedance point, x1,y1 - center of input stability circle, x2,y2 - cartesian coordinates on a Smith chart obtained from polar form, R - radius of unstable circle. This resulted in two plots Din(f) Dout(f). If circle was unstable inside, then D must be positive and maximized. If circle was unstable outside, then D must be negative and minimized. K-factor graph looked less informative, and probably was better indicator for oscillator design rather than amplifier design. Graphical representation with stability circles also helps to understand if unstable region "chases" your matching network impedance while frequency changes, or even rotates in opposite directions and "collide". Then you can try to change termination in some way to avoid this collision with unstable region.
 

    M

    Mabrok

    Points: 2
    Helpful Answer Positive Rating
Georgy.Moshkin said:
If simulation and prototype layout are totally the same
Click to expand...

Elements like the blocking caps in the supply line are ideal in simulation, which will create an ideal short. But real caps are not like that. Packing them all in parallel as shown here, in a very RF-ignorant way, will behave very differently. There is not even a via from top "ground" at the caps to backside ground, as far as I can see.

I agree that the layout looks totally completely wrong. For example, it make no sense to make the bias lines 50 Ohm (that should be narrow), and it makes no sense to make the RF lines that narrow (should be 50 Ohm). It all looks very wrong, dimensions and placement and assembly.
 

Here are some thoughts on what you already have:

impedance1.jpg


Here is what I've talked about:
impedance2.jpg


What if you just use 50 Ohm lines, two DC block capacitors.
Biasing will be done through thin 0.2mm lines with radial stubs (will be pretty large at 2.4GHz)
I think it will withstand your currents at room temperature.
If SMA connectors are 50 Ohm and do not have any surprises, everything soldered well, you probably can measure some meaningful data.
I do not trust those lumped resistors and capacitors, I understand that at 2.4GHz size matters, but radial stub and thin line will provide less impact on input/output impedance than your "hairpins".
You can find out radial stub optimal radius from simulation. I would try butterfly shaped stub also, it probably will be "invisible" in a much larger band around 2.4GHz. I always use thinnest possible biasing line with radial stubs.
 

    M

    Mabrok

    Points: 2
    Helpful Answer Positive Rating
    K

    ktr

    Points: 2
    Helpful Answer Positive Rating
BigBoss said:
-Your layout looks weird.A Wide Microstrip Line then a very Narrow MS Line..It's unusual Impedance Matching.Have you ever simulated your layout in Momentum or similar EM Simulator ?I believe there are many errors in Design.
-If the PCB is Double Sided ( Bottom Side is completely GND ), connection method of Decoupling Capacitors is completely wrong.A single screw cannot provide a good GND connection.There must be many VIAs connected to Bottom Side ( GND )
-Decoupling Capacitors cannot be soldered as you wish.First small valued Capacitors then bigger valued ones.( find why ?)
-Connectors are also bad mounted.There have to be many VIAs around GND Connection of the Connectors so both side should be connected very well together
-Research and Inspire from similar PCBs of different Manufacturers.View attachment 165979
Click to expand...
@BigBoss If the PCB is Double Sided ( Bottom Side is completely GND ), connection method of Decoupling Capacitors is completely wrong.A single screw cannot provide a good GND connection.There must be many VIAs connected to Bottom Side ( GND). How if I use single screw on the center of the rectangular patch, and drill more vias (left them opened)? or need to use screws for the all vias?
 

Mabrok said:
Hi,

During my measurements for an RF power amplifier. Once I biased the device, I see overloaded on VNA screen. What can make this overloaded?



Note: My device consider as high power amplifier (Pout= 40 dBm), and I have used an attenuator of 20 dB between the output of the amplifier and port 2 of VNA.
Click to expand...
A VNA is usually designed to operate well with the maximum power that can come out of Port 1. Typically this is 0 dBm to +15 dBm. If you exceed this maximum value into Port 2 you'll either compress the receiver and get reduced gain answers or you'll fry the bridge and need a repair. I advise that you turn the port power on Port 1 down such that the power into Port 2 is reasonable.

Also if you need to calibrate out the attenuator on the Port 2 cable, you can do so using 2-port, One-Path calibration. This will give you S11 and S21 but not S22 or S12. This is because the one port cal is not done on Port 2 in this case. It is impossible to do a 1 port calibration through a pad with 20 dB or more attenuation so 2P-One path is a suitable option.
 

The two biasing lines are transmission lines and are part of the circuit. It would be helpful to look at the stability circles for the device and see what is going on at the oscillation frequency. You normally want to arrange for the output match to follow some trajectory which delivers stable gain over some range and then intentionally collapses to stable points with minimal gain on either side of the desired range. This might require ferrites or fan stubs or any number of other tricks. The input should be nominally conjugate matched.
 
  • Like
Reactions: Mabrok

    M

    Mabrok

    Points: 2
    Helpful Answer Positive Rating
Georgy.Moshkin said:
Here are some thoughts on what you already have:

View attachment 166005

Here is what I've talked about:
View attachment 166006

What if you just use 50 Ohm lines, two DC block capacitors.
Biasing will be done through thin 0.2mm lines with radial stubs (will be pretty large at 2.4GHz)
I think it will withstand your currents at room temperature.
If SMA connectors are 50 Ohm and do not have any surprises, everything soldered well, you probably can measure some meaningful data.
I do not trust those lumped resistors and capacitors, I understand that at 2.4GHz size matters, but radial stub and thin line will provide less impact on input/output impedance than your "hairpins".
You can find out radial stub optimal radius from simulation. I would try butterfly shaped stub also, it probably will be "invisible" in a much larger band around 2.4GHz. I always use thinnest possible biasing line with radial stubs.
Click to expand...
Hello Georgy,

Came across this thread in the forum. It is surprisingly informative about RF layout techniques. I want to get your opinion on some questions.

-How important are the stitching vias along the RF line in this design? Should there be; or is it fine like this?
-Why would you use radial stubs in this frequency? I thought rule-of-thumb for radial stubs were X-Band or higher.
-What is your opinion on the legs of the SMA connector? I believe the connection should be done with more solder.

Kind Regards,

ktr
 

ktr said:
-How important are the stitching vias along the RF line in this design? Should there be; or is it fine like this?
-Why would you use radial stubs in this frequency? I thought rule-of-thumb for radial stubs were X-Band or higher.
-What is your opinion on the legs of the SMA connector? I believe the connection should be done with more solder.
Click to expand...
Stitching vias are used with coplanar+ground structures to avoid parasitic resonances of the top copper pours. The shown PCB is apparently manufactured without through-plating, no chance to have vias. Vias would be urgently required for the bypass capacitors in the first place.

Radial stubs have lambda/4 radius, e.g. 15 to 20 mm at 2.45 GHz on low/medium Er substrate. Thus feasible if you have some room.

SMA edge connectors would preferably get all ground pins connected. Not feasible without-through plating.
 

FvM said:
Stitching vias are used with coplanar+ground structures to avoid parasitic resonances of the top copper pours. The shown PCB is apparently manufactured without through-plating, no chance to have vias. Vias would be urgently required for the bypass capacitors in the first place.

Radial stubs have lambda/4 radius, e.g. 15 to 20 mm at 2.45 GHz on low/medium Er substrate. Thus feasible if you have some room.

SMA edge connectors would preferably get all ground pins connected. Not feasible without-through plating.
Click to expand...
Apart from placing the capacitors in order with their resonance frequencies (going from small values to large); how would you place vias around them? an what rule-of-thumb would you use for via radius at this frequency (3.4 Ghz) ?
 

Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top