Configuration Registers within an FPGA

Hi,

Which is the best way to store/hold the state of the "settings/configuration" register within an FPGA that is part of a complex system?

This is what I am thinking:

Assuming a register frame of 100-bit length as follows, 012....XXXXXXX, where 012 are the first 3 bits that I use for control the flow of the info. Let's say: if the 012 = "010" the system goes in configuration mode where XXXXXXX bits are information to config the system and if the value is "001" the system goes in the readout mode and the XXXXX bits are the readout information. Is this a correct way to handle the settings of the whole configuration system?

I am thinking to store and manipulate this frame by using the embedded RAM of the FPGA, or simply by using a signal register as follows:
signal config_data: std_logic_vector(99 downto 0) := (others => '0');

Which is the best and efficient way to do this?

Many thanks in advance,
Vlad

A register is definitely the more efficient way to go. If you use RAM, you're going to have to use an entire RAM block (size depends on your FPGA) to store just 100 bits.

While flops/registers are the most efficient, they are also somewhat real-estate costly.
For Xilinx series 7 FPGAs there are Block-RAMs and Distributed-RAMs.
For your case I wouldn't use a block RAM for the reason given above by Barry. But if you think 100 bits are costly for you and if you are using a Xilinx 7 series family FPGA, then distributed RAMs are also a good alternative (I generally use D-RAMs to implement very small sized FIFOs).

If it's for control then using a RAM won't work. Control bits must be continuously controlled not controlled sometimes while the RAM address is pointing to that control word.

If you have 1 address RAMs that are N-bits wide then you won't have a problem with the address changing, but then the "RAM" isn't a RAM anymore, it looks just like an N-bit wide register.

Dear all,

Many thanks for your answers, I will use a generic signal register then. It seems to be the easiest and most efficient way. By the way, it will be a Xilinx 7-series FPGA.

Cheers,
Vlad