Some questions about symmetric OTA optimization discussed in the book by David Binkley

I have following questions:
1. Why does the pole frequency at the drain of M5 define the BW, not the one at the output terminal?
In my circuit, the pole frequency at the output terminal is the dominant one (CL = 2pF), so it defines the BW.
I compared to another example in the book, i.e., folded cascode. it is the same, the output terminal is not considered as the dominant pole.
Is there any reason for this? am I missing something here?

2. In all three cases of optimization, i.e., DC, AC, balanced, all NMOS are equally sized and biased and all PMOS are equally sized and biased. See picture below.
This means that the current mirrors could have high gm/Id, i.e., in DC optimized case.
Does it make sense to have a good design?
It is quite the opposite of my supervisor told me that the current mirror must have low gm/Id, i.e., the MOSFET are in strong inversion.
For me, it is clear because in strong inversion we have better current copying result.

1. You can consider the mirror pole to be dominant if the OTA drives a very small capacitance, e.g. a transistor gate. If you have a substantial output load, then that load defines dominant pole (as its your case). The same goes for the folded cascode.

2. If high gm/id for the current mirror is good or not for your design is for you to decide, as you can see from the three optimization cases. Usually you should have resonably small gm/id for the current sources to reduce their noise when referred the OTA input.

arthorios said:

1. You can consider the mirror pole to be dominant if the OTA drives a very small capacitance, e.g. a transistor gate. If you have a substantial output load, then that load defines dominant pole (as its your case). The same goes for the folded cascode.

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Thanks for your answer.
I understand the answer for Q1.

arthorios said:

2. If high gm/id for the current mirror is good or not for your design is for you to decide, as you can see from the three optimization cases. Usually you should have resonably small gm/id for the current sources to reduce their noise when referred the OTA input.

Click to expand...

In all three cases, i.e., DC, AC, balanced, all NMOS are equally sized and biased and all PMOS are equally sized and biased.
It means we should not making any variation on sizing and biasing within all NMOS and within all PMOS, including the input device.
For example, M1-M2 must have the same sizing and biasing as M3-M4.
So I cannot size them independently.
Is my understanding correct?

melkord said:

In all three cases, i.e., DC, AC, balanced, all NMOS are equally sized and biased and all PMOS are equally sized and biased.
It means we should not making any variation on sizing and biasing within all NMOS and within all PMOS, including the input device.
For example, M1-M2 must have the same sizing and biasing as M3-M4.
So I cannot size them independently.
Is my understanding correct?

Click to expand...

No, once you understand how each transistor (pmos or nmos) affect the performance, you can size and bias them as you please. You should also take into consideration matching while doing this of course. If there is any restriction about the sizes/biasing of this example, it relates to the optimization suggested in the book.

arthorios said:

No, once you understand how each transistor (pmos or nmos) affect the performance, you can size and bias them as you please. You should also take into consideration matching while doing this of course. If there is any restriction about the sizes/biasing of this example, it relates to the optimization suggested in the book.

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maybe I should rephrase my question.
Why the book limit the design by making the input devices have the same size and bias as other devices, e.g., current mirror?
Is there any reason for this?
By doing this, do we really get an optimum design, compare to tuning input device and current mirror device independently?
The fact that the book use that limitation realy bothers me.
I appreciate it if you or someone else can shed some light about the motivation of doing so.

Of course, I can not say why the book limits the sizing to all equal dimensions for N and P transistors, I haven't read the book. But you will do yourself a disservice if you blindly do so.If you set your optimization goal - for example min current consumption to achieve a bandwidth, then you are free to optimize the transistor sizes anyway you see fit to achieve that goal.
Obviously, also the mirror pole should not be your dominant pole. It is the output pole that should dominate and by a lot. This way you can control the stability of the OTA in closed loop configuration. Just from the numbers in the tables assuming your 2pF load - the output pole is at 1.6MHz, while the mirror pole is at 350MHz for the AC case.

sutapanaki said:

Of course, I can not say why the book limits the sizing to all equal dimensions for N and P transistors, I haven't read the book. But you will do yourself a disservice if you blindly do so.If you set your optimization goal - for example min current consumption to achieve a bandwidth, then you are free to optimize the transistor sizes anyway you see fit to achieve that goal.

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Understood. It just really bothers me sometimes when the literature does not explain the motivation or the assumptions used to lead the author to the conclusion. Once I found a transfer function that is different with the result I derived. After more that two weeks, I realized the assumptions that was not mentioned. If I use this assumption which was not obvious, at least, for me, I got the same transfer function.

sutapanaki said:

Obviously, also the mirror pole should not be your dominant pole. It is the output pole that should dominate and by a lot. This way you can control the stability of the OTA in closed loop configuration. Just from the numbers in the tables assuming your 2pF load - the output pole is at 1.6MHz, while the mirror pole is at 350MHz for the AC case.

Click to expand...

Yes, I got it. Thank you.