melkord
Full Member level 3
![Full Member level 3](/styles/images/ranks/elevel3.gif)
I have following questions:
1. Why does the pole frequency at the drain of M5 define the BW, not the one at the output terminal?
In my circuit, the pole frequency at the output terminal is the dominant one (CL = 2pF), so it defines the BW.
I compared to another example in the book, i.e., folded cascode. it is the same, the output terminal is not considered as the dominant pole.
Is there any reason for this? am I missing something here?
2. In all three cases of optimization, i.e., DC, AC, balanced, all NMOS are equally sized and biased and all PMOS are equally sized and biased. See picture below.
This means that the current mirrors could have high gm/Id, i.e., in DC optimized case.
Does it make sense to have a good design?
It is quite the opposite of my supervisor told me that the current mirror must have low gm/Id, i.e., the MOSFET are in strong inversion.
For me, it is clear because in strong inversion we have better current copying result.
1. Why does the pole frequency at the drain of M5 define the BW, not the one at the output terminal?
In my circuit, the pole frequency at the output terminal is the dominant one (CL = 2pF), so it defines the BW.
I compared to another example in the book, i.e., folded cascode. it is the same, the output terminal is not considered as the dominant pole.
Is there any reason for this? am I missing something here?
2. In all three cases of optimization, i.e., DC, AC, balanced, all NMOS are equally sized and biased and all PMOS are equally sized and biased. See picture below.
This means that the current mirrors could have high gm/Id, i.e., in DC optimized case.
Does it make sense to have a good design?
It is quite the opposite of my supervisor told me that the current mirror must have low gm/Id, i.e., the MOSFET are in strong inversion.
For me, it is clear because in strong inversion we have better current copying result.