Mabrok
Full Member level 4
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The used substrate is roger 5880 with Er = 2.20 and h= 0.79 mm. So based on these values, the width of 50 ohm biasing line is 2.5 mm. The transistor used is CGH40010F high power transistor (10 watt) provided by cree company (place on the middle of the board). This type of transistors is designed to be mounted directly on the heatsink for source ground connection. For DC blocking, I use the commercial one from keysight technology (Agilent 11742A blocking capacitor). I do not understand "put biasing further away"? As the biasing line are 50 ohm quarter-wavelength connected at the gate and drain terminals of the transistor.Biasing lines do not look good. If those are 50 Ohm SMA connectors, microstrip looks too thin. Probably it is better to put input and output biasing farther away. I really would recommend to order some generic FR4 1.0mm boards manufactured at PCB fab based on your layout, with nice vias and everything, and you can put several prototypes on a single board, and obtain good results much easier. You can even put some resonator and estimate dielectric constant. I do not see what transistor do you use. I only familiar with low power FETs, many of them usually are stable if terminated with 50 Ohm (unstable circle boundaries are very far from center) and source pin is grounded very well with VIAS on a relatively thin substrate, for example 1.0mm or thinner FR4. Same transistors oscillate easily if termination is far from 50 Ohm, or there is bad grounding, when substrate is too thick and/or vias are too far from source pins, unstable circles are quickly "moved" to the center of Smith chart.
I would use radial quarter wave stubs for biasing, use thinnest possible biasing lines. On FR4 with Er=4.5 H=1.0mm main 50Ohm line width is 1.85mm. Biasing line may be around 0.3mm thick, quarterwave length between 50Ohm line and radial stub will be 18mm.
The only problem would left is finding good capacitors for DC blocking, or using special ones which are pretty expensive.
Possible design:
1) 4x4cm ground area around transistor on top layer, with many vias around source pins. Input and output lines are GCPW lines.
2) rounded transition from GCPW to microstrip on the edges of 4x4cm ground area. Both for input and output.
3) 0.2 mm thin biasing lines with radial stubs.
4) commercial DC block capacitors somewhere near SMA connectors.
On a FR4 substrate at 2.4GHz it will perform pretty the same even if Er will be 3.5 or 5.5, with or without solder mask, with high or low dielectric losses. Phase length and characteristic impedance do not change much at 2.4GHz. You probably will get more differences from how SMA connectors and transistor was soldered. If every component is ok and layout arrangement is good, and you checked stability circles, then there will be no impedance "swirling" around Smith chart through unstable regions of transistor as dielectric constant changes or if you connect SMA cables with different length or something like that.
Large copper area around transistor will help to dissipate more heat, putting thin biasing lines away from transistor gives lower temperature and higher possible currents (https://www.eeweb.com/tools/external-pcb-trace-max-current/), minimizes input to output coupling and forming of unwanted parallel feedback oscillator.