Georgy.Moshkin
Full Member level 5
What are best FPGA/CPLD options to build such frame grabber?
Requirements:
- support for 8mp mipi csi camera sensor, sony imx series or similar high resolution sensor
- no frame preview is required (no screen), only raw mipi csi data without processing
- save single frame to internal RAM on trigger signal with low latency, trigger signal speed may be around 1 FPS or slower
- built in or external DDR frame buffer
- readout of frame-buffer using slow interface (spi, rs232, etc.)
Is it possible to build using cheapest Lattice's machxo2 or machxo3 or similar FPGA product with some DDR memory?
Need some bare-bone architecture: after power up mipi csi camera sensor is configured to output continuous stream. On a trigger signal, one frame of this stream is saved to RAM in raw format. External PC read-outs this raw frame buffer through slow speed interface and perform further processing.
Requirements:
- support for 8mp mipi csi camera sensor, sony imx series or similar high resolution sensor
- no frame preview is required (no screen), only raw mipi csi data without processing
- save single frame to internal RAM on trigger signal with low latency, trigger signal speed may be around 1 FPS or slower
- built in or external DDR frame buffer
- readout of frame-buffer using slow interface (spi, rs232, etc.)
Is it possible to build using cheapest Lattice's machxo2 or machxo3 or similar FPGA product with some DDR memory?
Need some bare-bone architecture: after power up mipi csi camera sensor is configured to output continuous stream. On a trigger signal, one frame of this stream is saved to RAM in raw format. External PC read-outs this raw frame buffer through slow speed interface and perform further processing.