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Issues with GDSII import

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adnan_zaman

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Hello Everyone,

I have a P&R layout that I have created using IC compiler with the SAED EDK90nm design kit. Then I made a GDSII file from it and tried to import it both in cadence virtuoso and synopsys custom designer. First, I have created a library and attached it to the technology library SAED_PDK_90 (it contains different layer information). While streaming in the GDSII, i have used saed_pdk90_layer.map file found in the design kit. In my Layout, there are different cells like, "A022X1", "INVX0" etc. But, after streaming in when I open the layout in virtuoso/custom designer, It only shows the metal layers and vias, it doesn't show the cells. The warning I see is, "WARNING (XSTRM-267): The referenced cell "AO22X1" was not found. The OpenAccess design data was created for this cell without any reference. Ensure that the referenced cell exists and library is defined in the cds.lib file." I found similar message in custom designer.

Now, my question is, why the cells don't show up as cells? Do I need to include/attach any other libraries/technology files?

Any kind of help will be greatly appreciated.

Thanks in advance.
 

Is it possible, that you did not streamout all levels of hierarchy? I remember, that the command in ICC have such options. Check the man for this command.
 

oratie said:
Is it possible, that you did not streamout all levels of hierarchy? I remember, that the command in ICC have such options. Check the man for this command.
Click to expand...

It is not about hierarchy.

Physical synthesis doesn't have/need any information about the full layout of the cells, it only needs to know the abstract view. So it doesn't know how to export it in the first place. When you export the gds, you have to point to the standard cell gds file, then the tool will merge the two of them into one.

Now, because this is an academic library, I am not certain there is a gds for the cells. You will have to check.
 

Incorrect. The Milkyway database (that IC compiler uses) may contain all needed info about layout of the cells (in different views FRAM, CEL). So, it is possible that not all hierarchy levels were written into GDS. Option is child_depth.
 

oratie said:
Incorrect. The Milkyway database (that IC compiler uses) may contain all needed info about layout of the cells (in different views FRAM, CEL). So, it is possible that not all hierarchy levels were written into GDS. Option is child_depth.
Click to expand...

Huh. If this is the case, do we know if the SAED 90nm library has a layout view in it? Being academic and all, I wouldn't be surprised if it has nothing inside.

- - - Updated - - -

another approach is to make the merging on the environment you are using (virtuoso?). It might be easier. And it definitely takes gds as input to stream in.
 

Hello ThisIsNotSam, Thanks for your reply.

Can you please elaborate on the merging on the environment that you mentioned?

And, secondly, I'm using the custom compiler to import the GDSII file generated in the IC compiler (I'm trying only synopsis flow this time). There's an option where it asks for reference library file. I'm not sure which library file it is asking for, as I tried the lib file located in the standard cell directory. It shows error message as,
"ERROR: (IMPORT_STREAM-43): Invalid character '/' in input name: /****************************************************************
******."
I'm also attaching the screenshot of that option tab. Can you please advice on this regard?

Thanks!

stream_in_cc.JPG
 

on virtuoso you can import 2 gds files: one from your design and one from std cell library. the tool recognizes that your design has instances of the std cell library and it will merge the two for you in a single gds file. there are many steps to get this done, which include having virtuoso configured for your specific technology. when it works, this flow is very stable.

what you are trying to do is exactly the same but in a different tool. I have never used custom compiler, so I can't comment on what information you have to pass to the tool on that `library file' box.
 
I suppose, that you should not specify .lib file. It contains timing info, but you need layout data. It can be Milkyway library, or NDM, or OA. Check what you have.
 
Thank you @ThisIsNotSam and @oratie. Eventually, I found a way to resolve the issues mentioned above. Now, I'm struggling with the issue in the case of simulating the schematic. After I imported the schematic using veriliog import-in, I have a symbol view and schematic view of the circuit( inv). I'll add pictures here to explain the hierarchy and then I'll state the problem I'm facing.

sim_lvl_1.PNG

Fig. 1: Hierarchy 1 (symbol)

sim_lvl_2.PNG

Fig. 2: Hierarchy 2 (schematic -- generated after I imported from ICC)

sim_lvl_3.PNG

Fig. 3: Hierarchy 3 (Standard cell to which schematic and symbol is bounded)

Here, I created a new cell and connected voltages and gnd as shown in Fig. 1. You can descend on that symbol to check the other hierarchies as shown in Fig. 2 and Fig. 3 respectively. Now, when I try to do the simulation, the HSPICE simulation runs without errors but I get the following warnings:

Checking "my_lib_32/inv/schematic"
[warning] Floating I/O Pins
I/O pin 'VDD' is floating
I/O pin 'VSS' is floating
0 Error(s),2 Warning(s),0 Message(s) found in "my_lib_32/inv/schematic"

Which is also visible from Fig. 2. So, eventually, I get an incorrect output though there are no errors or warnings from the top-level ( the warning generates from the second level).

I tried to do drc, lvs and pex. Everything worked correctly using the same schematic. only when I'm trying to simulate, it is showing this warning.

I'm also attaching the netlist the simulator is generating, it seems okay to me.

*Custom Compiler Version M-2017.03-SP1-1
*Thu Oct 22 15:45:23 2020

.GLOBAL gnd!
********************************************************************************
* Library : saed32nm_stdcell_hvt_oa
* Cell : INVX1_HVT
* View : schematic
* View Search List : hspice hspiceD schematic spice veriloga
* View Stop List : hspice hspiceD
********************************************************************************
.subckt invx1_hvt a y
xp y a vdd vdd p105_hvt w=0.8u l=0.03u nf=1.0 m=1
xn y a vss vss n105_hvt w=0.42u l=0.03u nf=1.0 m=1
.ends invx1_hvt

********************************************************************************
* Library : my_lib_32
* Cell : inv
* View : schematic
* View Search List : hspice hspiceD schematic spice veriloga
* View Stop List : hspice hspiceD
********************************************************************************
.subckt inv o1 i1 vdd vss
xu2 i1 o1 invx1_hvt
.ends inv

********************************************************************************
* Library : my_lib_32
* Cell : inv_test_2
* View : schematic
* View Search List : hspice hspiceD schematic spice veriloga
* View Stop List : hspice hspiceD
********************************************************************************
r16 o1 gnd! r=1G
xi3 o1 i1 vdd gnd! inv
v12 vdd gnd! dc=1
v8 i1 gnd! dc=0 pulse ( 0 1 0 5p 5p 5n 10n )

In this circumstance, do you guys have any suggestions for me? I would really appreciate your help.

Thanks
 

Attachments

  • sim_lvl_1.PNG
    sim_lvl_1.PNG
    11.2 KB · Views: 186

According to your netlist you have nets vdd/vss inside subckt inv. But there are no connections to them. You have defined as global gnd! only.

Should be ".global vdd vss" ?
 
either you make vdd global or you make it an input of the INV subckt. the point is that what oratie said is the issue: the cell is not seeing the power supply internally.
 
Thank you, everyone!

I just have one issue left. When I import the GDSII file (generated by IC Compiler) into Custom Compiler and run LVS, I see that pin labels are not preserved. When I put the pin labels it passes the LVS and everything checks out fine. But, I want to avoid this manual pin labeling.

Is there any way I can export GDSII or any other file format, so that pin information, i.e., labels are preserved?

Thanks
Adnan
 

GDS-II has no idea about "pins" or their Cadence
properties (which is how connectivity is expressed).

As a work-saver I will make a layout cell containing
the pins associated with the pad ring (there should
be no others in a top-level product die), place the
empty cell (e.g. top_pins/layout/current) at 0,0 of
the top level layout and edit-in-place creating all
of the pin polygons (on appropriate layer) and
labels. I like to place pins as minuscule rectangles
at the pad centers, so later their X,Y properties can
be "harvested" for probe card coords, but that's for
much later.

Once the pad-ring pins cell is made, I will flatten
it by one level to bring the pins onto the top level.
But the top_pins cell remains in the library, for
later use. Such as when you stream back in the
layout, having lost all but the raw polygon layer /
purpose info of every pin - just place the top_pins
cell again, and flatten it again, if you want to (say)
rerun extract and LVS, or to get an analog_extracted
view with LVS-valid pin correspondence.
 
adnan_zaman said:
I just have one issue left. When I import the GDSII file (generated by IC Compiler) into Custom Compiler and run LVS, I see that pin labels are not preserved.
Click to expand...
In Innovus you can write any label you want and associate any datatype to it. Maybe ICC has something similar but I wouldn't know, ICC is not something I use regularly. Maybe look for a create_label command or create_text, something like that.
 
Thank you everyone! Finally, I was able to complete the total flow. It is not pretty I must say!

If anyone needs help, I will be more than happy to help!

Thanks again.
 

adnan_zaman said:
Thank you @ThisIsNotSam and @oratie. Eventually, I found a way to resolve the issues mentioned above. Now, I'm struggling with the issue in the case of simulating the schematic. After I imported the schematic using veriliog import-in, I have a symbol view and schematic view of the circuit( inv). I'll add pictures here to explain the hierarchy and then I'll state the problem I'm facing.

View attachment 165063
Fig. 1: Hierarchy 1 (symbol)

View attachment 165060
Fig. 2: Hierarchy 2 (schematic -- generated after I imported from ICC)

View attachment 165061
Fig. 3: Hierarchy 3 (Standard cell to which schematic and symbol is bounded)

Here, I created a new cell and connected voltages and gnd as shown in Fig. 1. You can descend on that symbol to check the other hierarchies as shown in Fig. 2 and Fig. 3 respectively. Now, when I try to do the simulation, the HSPICE simulation runs without errors but I get the following warnings:

Checking "my_lib_32/inv/schematic"
[warning] Floating I/O Pins
I/O pin 'VDD' is floating
I/O pin 'VSS' is floating
0 Error(s),2 Warning(s),0 Message(s) found in "my_lib_32/inv/schematic"

Which is also visible from Fig. 2. So, eventually, I get an incorrect output though there are no errors or warnings from the top-level ( the warning generates from the second level).

I tried to do drc, lvs and pex. Everything worked correctly using the same schematic. only when I'm trying to simulate, it is showing this warning.

I'm also attaching the netlist the simulator is generating, it seems okay to me.

*Custom Compiler Version M-2017.03-SP1-1
*Thu Oct 22 15:45:23 2020

.GLOBAL gnd!
********************************************************************************
* Library : saed32nm_stdcell_hvt_oa
* Cell : INVX1_HVT
* View : schematic
* View Search List : hspice hspiceD schematic spice veriloga
* View Stop List : hspice hspiceD
********************************************************************************
.subckt invx1_hvt a y
xp y a vdd vdd p105_hvt w=0.8u l=0.03u nf=1.0 m=1
xn y a vss vss n105_hvt w=0.42u l=0.03u nf=1.0 m=1
.ends invx1_hvt

********************************************************************************
* Library : my_lib_32
* Cell : inv
* View : schematic
* View Search List : hspice hspiceD schematic spice veriloga
* View Stop List : hspice hspiceD
********************************************************************************
.subckt inv o1 i1 vdd vss
xu2 i1 o1 invx1_hvt
.ends inv

********************************************************************************
* Library : my_lib_32
* Cell : inv_test_2
* View : schematic
* View Search List : hspice hspiceD schematic spice veriloga
* View Stop List : hspice hspiceD
********************************************************************************
r16 o1 gnd! r=1G
xi3 o1 i1 vdd gnd! inv
v12 vdd gnd! dc=1
v8 i1 gnd! dc=0 pulse ( 0 1 0 5p 5p 5n 10n )

In this circumstance, do you guys have any suggestions for me? I would really appreciate your help.

Thanks
Click to expand...
Dear sir, I've met the problem that cells can not be shown in virtuoso and I've tried some suggestions under this thread but it didn't work out. Since you have solved it, would you mind giving some more specific instructions about importing ICC gds and showing all cells in virtuoso, I'm really curious about what files I really need to make this work and ways to deal with them.

Best regards!
 

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