Timing violations

Hi! Can you please help? In my block, I have one Scan clock and One Functional clock. There are two generated clocks from the Functional clock and one generated clock from the Scan clock. Now, most of the setup violations (reg2reg) are coming from the launch flop triggered by generated clock of Scan clock and capture flop triggered by generated clock of Functional clock or vice versa. Are these valid timing paths? SDC has these Functional clock and SCAN clock declared as asynchronous, but not the generated clocks. If I create two clock groups as below and declare them as asynchronous, then those paths don’t show up and this solves my problem. Is this correct?

Group 1- {Scan clock, Generated clock from Scan clock}

Group 2: {Func clock, Generated clock from Func clock}

In the real silicon, will both generated clocks operate at the same time? If no - your proposal about clock groups is correct.