Effect of transition time on power consumption

How transition time affetcs the power consumption in Physical designing

Not specific to ASICs, but when you’re turning on a MOSFET, power is dissipated during the transition. Remember that power dissipation is the voltage across the device times the current through the device. When the device is off voltage is maximum and current is minimum==> power =low. When the device is fully on, current is maximum and voltage is minimum ==> power = low. During the turn-on transition voltage drops and current rises and power increases. power is maximum in the middle of the transition. The same is true during turn-off.

Hi,

barry is correct ... for some kind of resistive loads.

but maybe your question is about ASIC inside signal transitions.
Inside an ASIC/FPGA/Logic IC... there is not much resistive load.
For transitions without resistive load - just for the capacitve load - I guess the transition time does not matter.
I´m not 100% sure. But I guess when the transition time decreases the current increases... the result should be identical averaged (integrated) current.

Klaus

Switching charge taken from the supply (or ground)
goes to several things. One is the capacitive gate + wire
load, this is independent of transition time, Q=CV and
I=CVf. The other is shoot-through in the driver output
(and predriver) totem pole. This is a charge slug that
persists for the time that the predriver takes to slew
the final stage gates from Vdd to VTN (ish) and Vss
to VTP. This drive is an element of transition time but
not much affected by it. The thirs place for charge-take
is the driven gate. Here, slow transitions keep the front
stage(s) longer in the linear, dissipative region of the
VIN-VOUT transfer characteristic. Transition time here
goes directly to that gate's short term and average
power dissipation, call it IDsat*(VDD-VTN-VTP)*freq/SR
(I'd bet you could find a more blessed derivation in
some paper somewhere but that's roughly the
mechanics of it).

riti said:

How transition time affetcs the power consumption in Physical designing

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If you're particularly asking about drc parameters such as max_trans/target_max_trans during the physical stage, then steeper the transition requirement, more data path/clock tree buffers and gate-upsizing is needed. This eventually increases the dynamic power dissipation of the design, dominantly in the clock-tree.

ranaya said:

If you're particularly asking about drc parameters such as max_trans/target_max_trans during the physical stage, then steeper the transition requirement, more data path/clock tree buffers and gate-upsizing is needed. This eventually increases the dynamic power dissipation of the design, dominantly in the clock-tree.

Click to expand...

I think it will increase static power not dynamic power as dynamic power depends on fCV2. please correct me if i am understanding wrong.

Buffers are upsized -> buffers internal C is higher -> internal cell power (part of total dynamic power) is higher. And, of course, cell leakage power is higher, as well.

think of an inverter. the input of the inverter is a very slow transition. it comes a point when both the nmos and the pmos are conducting, thus causing a short circuit current. this is undesirable. often it is worth to increase the driver cell to fix the slow transition. in isolation, the new buffed up driver and load now consume more. but because the transition is faster, the aggregate circuit consumes less. I hope this is clear.