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Filler cell X1 in 28nm node

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stevenv07

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Hello,

After doing placement standard cell and routing, I inserted filler cells. In 28nm TSMC technology node, there is no filler cell width X1, but there are many gap with width of X1. So, Innovus and ICC cannot fill gaps with filler cells X2, X4, etc. Can anyone help me to explain this issue and fix this?

Thanks in advance!

Steve.
 

For ICC
set_lib_cell_spacing_label -names {X} ...
set_spacing_label_rule -labels {X X} {1 1}
place_opt

insert_stdcell_filler -no_1x
 

for innovus, you can try the command that adds decaps. it has more options/parameters than the add filler. maybe you will get lucky.
 

I mean in my design, there are many gaps of X1 between standard cells, but the library 28nm does not have filler cell X1. What should I do with filler cells X2, X4, etc.

@oratie, can we apply your approach to all kinds of cells in the library when the design is big?

Many thanks!
 

stevenv07 said:
@oratie, can we apply your approach to all kinds of cells in the library when the design is big?
Click to expand...

Sure. You must apply set_spacing_label_rule for all library cells (std cells). So, the placer will avoid 1x spacing between cells.
 
I am still scratching my head on this one. I have worked with TSMC 28 technology and the fillers were there. (there are like 5 flavors of the same 28nm node, so maybe your std cell library is different).
 

I have one more question: why does the horizontal pitch get the value of 0.135 um in the technology file?(size 0.135 by 0.7). The std. Cell widths get a multiple of 0.14um. Std cells will be placed off-grid by pnr tool?

Many thanks.
 

Maybe tech file should be tuned for this std cell library? Usually, the foundry deliver tech file with install script, so you can tune it.
 
oratie said:
Maybe tech file should be tuned for this std cell library? Usually, the foundry deliver tech file with install script, so you can tune it.
Click to expand...
this is likely the reason. there could also be some issue with shrink factor. say, the original technology is 65nm, but the foundry later started providing a shrunk version at 60nm as a process upgrade.
 

oratie said:
Maybe tech file should be tuned for this std cell library? Usually, the foundry deliver tech file with install script, so you can tune it.
Click to expand...

I wil try it. Thank you very much.
 

stevenv07 said:
I wil try it. Thank you very much.
Click to expand...
After the placement, try this in Innovus :

# Adding physical cells in incremental manner !
# I have a filler set FIL1R, FILE3R etc....
getFillerMode -quiet
addFiller -cell FILE3R -prefix FILLER
addFiller -cell FILE3R -fixDRC
addFiller -cell FIL1R -prefix FILLER
verifyConnectivity -type all -error 1000 -warning 50
saveDesign ${DESIGN_NAME}
 
For 28nm tsmc library, we dont have filler-1. We only have filler2, filler3, filler4, etc.

Does innovus have any command to make a gap (if any) between stdcell at least 2X? Not 1X.

Many thanks
 

In addition to what @ThisIsNotSam said,

setPlaceMode -place_detail_legalization_inst_gap 2 //specify two sites fillers or larger instead of 1 site filler
setFillerMode -core {FILL16 FILL8 FILL4 FILL3 FILL2} -fitGap true
place_opt_design

Another way (?):
setPlaceMode -fillerGapMinGap <min_gap_spacing in micron> -fillerGapEffort {medium | high}
 
ranaya said:
In addition to what @ThisIsNotSam said,

setPlaceMode -place_detail_legalization_inst_gap 2 //specify two sites fillers or larger instead of 1 site filler
setFillerMode -core {FILL16 FILL8 FILL4 FILL3 FILL2} -fitGap true
place_opt_design

Another way (?):
setPlaceMode -fillerGapMinGap <min_gap_spacing in micron> -fillerGapEffort {medium | high}
Click to expand...

I see, that's good solution.
 
stevenv07 said:
I have one more question: why does the horizontal pitch get the value of 0.135 um in the technology file?(size 0.135 by 0.7). The std. Cell widths get a multiple of 0.14um. Std cells will be placed off-grid by pnr tool?

Many thanks.
Click to expand...
the tool is taking the values from one of the site among the others, tell the tool to specifically take 0.140 *0.7
 

After placement, the gap between standard cells is 2X (i.e., 2*0.14um). However, after applying CTS, the Innovus tool added many clock buffers, and a lot of 1X gaps are still left. How can I fix this problem?
 

During postRoute, the Innovus up-sizes and down-size instances to fix timing violations, it will cause x1 gaps. Can we use place_opt to fix these gaps?
 

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