nlulani
Junior Member level 3
Hello all,
Here I am working on the design of some DSP algorithms,
as an initiative i have designed a simple Ist order low pass filter IIR filter, the functional verification and simulation results are done well thoroughly using MATLAB and Testbench development.
the actual code is also synthesizable (successfully)
Target Device : x2v80
Target Package : fg256
Target Speed : -6
though the target chosen has much more capability then the required for this particular code, but because my aim is to design more complicated DSP algorithms so i have chosen this target: a look at the map report :
Design Summary
--------------
Number of errors: 0
Number of warnings: 0
Logic Utilization:
Number of Slice Flip Flops: 29 out of 1,024 2%
Number of 4 input LUTs: 60 out of 1,024 5%
Logic Distribution:
Number of occupied Slices: 38 out of 512 7%
Number of Slices containing only related logic: 38 out of 38 100%
Number of Slices containing unrelated logic: 0 out of 38 0%
*See NOTES below for an explanation of the effects of unrelated logic
Total Number 4 input LUTs: 60 out of 1,024 5%
Number of bonded IOBs: 47 out of 120 39%
IOB Flip Flops: 45
Number of MULT18X18s: 3 out of 8 37%
Number of GCLKs: 1 out of 16 6%
so its clear that the same target is much more capable then its power utilised here
now i need to verify my results on a hardware, so i would like to hear from anyone who can tell me the best possible hardware available for verification with obviosuly ADC and DAC on boards.
please reply me with some economic solution for my problem
thanks and best wishes
Nitin Lulani
Here I am working on the design of some DSP algorithms,
as an initiative i have designed a simple Ist order low pass filter IIR filter, the functional verification and simulation results are done well thoroughly using MATLAB and Testbench development.
the actual code is also synthesizable (successfully)
Target Device : x2v80
Target Package : fg256
Target Speed : -6
though the target chosen has much more capability then the required for this particular code, but because my aim is to design more complicated DSP algorithms so i have chosen this target: a look at the map report :
Design Summary
--------------
Number of errors: 0
Number of warnings: 0
Logic Utilization:
Number of Slice Flip Flops: 29 out of 1,024 2%
Number of 4 input LUTs: 60 out of 1,024 5%
Logic Distribution:
Number of occupied Slices: 38 out of 512 7%
Number of Slices containing only related logic: 38 out of 38 100%
Number of Slices containing unrelated logic: 0 out of 38 0%
*See NOTES below for an explanation of the effects of unrelated logic
Total Number 4 input LUTs: 60 out of 1,024 5%
Number of bonded IOBs: 47 out of 120 39%
IOB Flip Flops: 45
Number of MULT18X18s: 3 out of 8 37%
Number of GCLKs: 1 out of 16 6%
so its clear that the same target is much more capable then its power utilised here
now i need to verify my results on a hardware, so i would like to hear from anyone who can tell me the best possible hardware available for verification with obviosuly ADC and DAC on boards.
please reply me with some economic solution for my problem
thanks and best wishes
Nitin Lulani