tahirsengine
Member level 3
The difference between '|' operator and keyword 'or'
Hi,
I have noticed that in Verilog literature, the symbol '|' is often used for OR operations. But at some other places the keyword 'or' is also used.
In most of the always blocks, the keyword 'or' is used, and in if statements, either '|' is used or '||' is used.
So functionally, what is the difference between the two, and where to use what.
Hi,
I have noticed that in Verilog literature, the symbol '|' is often used for OR operations. But at some other places the keyword 'or' is also used.
In most of the always blocks, the keyword 'or' is used, and in if statements, either '|' is used or '||' is used.
So functionally, what is the difference between the two, and where to use what.
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