Continue to Site

OpenCL vs VHDL running in FPGA

Status
Not open for further replies.
A

adwnis123

Full Member level 4
Full Member level 4
Joined
Jun 19, 2014
Messages
214
Helped
0
Reputation
0
Reaction score
1
Trophy points
18
Activity points
1,737
Hello,

If I "migrate" to OpeCL language for programming FPGA, will be any difference in speed running the "same" algorithm? I mean if I have an algorithm built in VHDL for Spartan 3E and the same algorithm implemented in OpenCL. Will I see any difference in speed? Is there any other difference practically between OpenCL and VHDL?

Thank you
 

Iirc, opencl requires a processor top control the system. Vhdl does not. OpenCL is a higher levelthan vhdl. So while you can probably Get a system up and running faster than vhdl, the vhdl solution will likely be smaller and run faster.

That's never a guarantee though. Like with any system, the end result is more down to the quality of the engineer writing it than the system used top create it.
 
Regarding your question.
Comparing VHDL and OpenCL as 2 languages is misleading.
OpenCL is MUCH more then just a "Higher Level" language. It's a complete framework that describes communication mechanisms between hosts and devices.

It's much better to compare HDL to HLS...

Will I see any difference in speed?
Click to expand...
It depends.
You can write very poor VHDL/Verilog code that will have low performance compared to machine generated HLS code.
But most of the time - a well written and optimized VHDL code will tend to run faster then HLS.

It's kind of comparing C to Assembler:
Can well hand written optimized Assembler code outperform compiled C ? Almost always.
Can you write Assembler code that performs worse then C code ? Sure, if you don't know you're doing.
 
Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top