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> im talking about equipment thats implemented on the chip.
Your question isn't very clear.
In traditional SCAN/ATPG methodology, the test-patterns come from an external device (test-console.) The on-chip hardware is very limited -- 1) some I/O drivers to receive the incoming pattern, and transmit the observed response. 2) SCAN registers to allow the external-console "set" the state of the entire chip (usually by means of serial scan-chains.) The SCAN registers can either be multiplexed D-flipflops, or level-sensitive latches, the foundry tells you which they support.
More recently, ASICs have gotten larger and larger (millions of gates), so test patterns have grown correspondingly. At some point, the time it takes to sweep a full ATPG-pattern through the device-under-test becomes uneconomical. So EDA-companies have come up with an alternative approach -- logic BIST (built-in-self-test.) In this methdology, the DFT-tool inserts an intelligent state-machine + control-logic into your design-netlist. The embedded state-machine generates the test-pattern, exercises the logic, then measures the logic's response to determine PASS/FAIL. This approach has the advantage of using very little data transmission over the I/O, and this also reduces test time. But of course, the logic-BIST controller adds a lot gates by itself (area overhead.) There are other variations on logic-BIST, but they all try to accomplish the same thing -- minimize the amount of external pattern-data needed to test a chip. (Basically, logic-BIST puts 'intelligence' in the chip. Traditional BIST keeps intelligence out of the chip, in the external tester-console.)
ATPG Generater generates the test vectors
but BIST approach seems to answer you better.
IST aproach uses LFSRs etc to generate the test patterns in the chip itsef.
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