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Hot NWELL warning in layout design

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Junus2012

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Dear friends,

I designed a matched array of PMOS differential amplifier, the input bulk contact of the the PMOS input transistors are not connected to VDD, but they are connected to the sources. Therefore I have made an NWELL, I put my matched PMOS there, and I made separate ND_Contacts in the well ans I connected the sources to it. I didn't merge the bulk contact to the source in the diffusion, should be that a problem ?

can I ignore this warning ?
 

What does hot nwell mean?

Maybe see if your current goes through the nwell instead of through the sources. Also, a drawing of the layout and connections will be helpful.
 
I’m not familiar with “ND_contact” what is that—n diffusion? If you have an Nwell tub around your devices, you need to ensure the nwell is stamped with an n+ diffusion ohmic contact. If the body and sources of the pfets are shorted together in schematic, contact the metal connection of the nwell contact to the metal connections of the source metal contacts on each of the fingers of the devices.

What kind of warning is this? DRC, LVS, or ERC?
 
thank you guys for your reply

Indeed I have ignored this warning and every thing is working fine. I believe now for ERC every well without VDD contact will be issued as a hot WELL, he doesn't care if it is connected to the source
 

Any NWELL you have connected like this will get flagged due to potential latch-up issues. Be sure to ring the NWELL with a PSUB contact ring. Also, try to keep these NWELLs as far away from ESD devices that you can.
 

rangermad said:
Any NWELL you have connected like this will get flagged due to potential latch-up issues. Be sure to ring the NWELL with a PSUB contact ring. Also, try to keep these NWELLs as far away from ESD devices that you can.
Click to expand...

Dear Range,

What you mean please by ESD ?
 

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