Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

clock domain crossing

Status
Not open for further replies.

peen1

Member level 2
Member level 2
Joined
Nov 2, 2004
Messages
47
Helped
1
Reputation
2
Reaction score
0
Trophy points
1,286
Activity points
495
How do you move data from a fast clock domain to a slow clock domain?

I understand that if you move from slow to fast you can double flop with fast clock or use the fast domain to catch the falling edge of the slow clock and then latch in the data.
 

clock domain crossing handshake

using two clock domain FIFO or buffer, several ways to design it, find them out in this forum.
 

    V

    Points: 2
    Helpful Answer Positive Rating
clock+domain+crossing

You also can use handshake as a simple way.
 
  • Like
Reactions: pdhama

    pdhama

    Points: 2
    Helpful Answer Positive Rating
passing clock domains handshake

still use fast clock to sample slow clock, then the delayed posedge of slow clock (this signal is synchronized to fast clock),if is signal is low, hold data in the slow domain , change the data output to fast clock domain only if this signal is high. In a word , avoiding changing data at the posedge of slow clock by holding the data under such occassions.
 

    V

    Points: 2
    Helpful Answer Positive Rating
clock doman

with faster clock domain in your design, you must define a efficient operation protocol for synchrony. the setup and hold time delay is key for consideration.
 

    V

    Points: 2
    Helpful Answer Positive Rating
cdc fast to slow clock domain

If we are taking about data lines then generally two techniques, using a protocol a simple protocol can work where an new data is indicated by a flag set and reset signal after data capture "u can use a flancter to do this". or the other ultimate choice is to use a async. FIFO. in both design you have to take care of metastability issue
 
  • Like
Reactions: pdhama

    pdhama

    Points: 2
    Helpful Answer Positive Rating
fast to slow clock domain crossing circuits

hand shake is proper for low speed data transfer
FIFO is more common and much faster, but add difficult to your design
 
  • Like
Reactions: pdhama

    pdhama

    Points: 2
    Helpful Answer Positive Rating
handshake crossing clock domain

If it is asyncronous signal , latch the i/p thru Flip Fliops (atleast 2 FF's) using Rx domain frequency .Here you will be losing 1 or 2 clks ,but probability of getting into Metastable is low.

Use FIFO for data lines & high speed transfers , but take care of FIFO depth.

Handshaking is also another method whereby one can sample the asyncronous signal using Handshaking signal from both the domains , here also speed matters at the cost of extra handshakes.
 
  • Like
Reactions: pdhama

    pdhama

    Points: 2
    Helpful Answer Positive Rating
clock domain crossing slower

Use level synchronize circuit
 
  • Like
Reactions: pdhama

    pdhama

    Points: 2
    Helpful Answer Positive Rating
passing data from slow to fast clock domains

There are various techniques to handle CDC.

i am attaching a paper on CDC.

go through it. its realy a good paper.
 

    V

    Points: 2
    Helpful Answer Positive Rating
move data from slow to fast clock domain

use FIFO
 

    V

    Points: 2
    Helpful Answer Positive Rating
clock domain handshaking

you can use two phase handshaking protocol to passing data from

one clock domain to another clock domain,

if you want high speed, use a asynchronous dual port fifo to

realize your dream.





peen1 said:
How do you move data from a fast clock domain to a slow clock domain?

I understand that if you move from slow to fast you can double flop with fast clock or use the fast domain to catch the falling edge of the slow clock and then latch in the data.

Added after 4 hours:


the attached file has some content on this problem.



peen1 said:
How do you move data from a fast clock domain to a slow clock domain?

I understand that if you move from slow to fast you can double flop with fast clock or use the fast domain to catch the falling edge of the slow clock and then latch in the data.
 
  • Like
Reactions: lorna8899

    lorna8899

    Points: 2
    Helpful Answer Positive Rating
    V

    Points: 2
    Helpful Answer Positive Rating
fast to slow crossing clock domains

use a dual port ram....and 2 counters to increment address....
increment the address of the read counter whenever not same as write counter
 

    V

    Points: 2
    Helpful Answer Positive Rating
signal crossing clock domains slower clock

Use handshake
 

    V

    Points: 2
    Helpful Answer Positive Rating
clock domain crossing fast to slow

Using handshake is the best option to avoid metastability.
 

    V

    Points: 2
    Helpful Answer Positive Rating
slow clock fast clock signal

Better go for Dual Port Ram or even Handshake Toggle Synchronizer....:D
 

    V

    Points: 2
    Helpful Answer Positive Rating
Use asynch fifo or handshake
 

    V

    Points: 2
    Helpful Answer Positive Rating
Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top