Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

[SOLVED] Convert from STD_LOGIC to integer in VHDL

Status
Not open for further replies.
M

MSAKARIM

Full Member level 3
Full Member level 3
Joined
Jun 2, 2015
Messages
154
Helped
1
Reputation
2
Reaction score
4
Trophy points
1,298
Activity points
2,528
Is this code right?, I need to convert from STD_LOGIC to integer( to add those integers) and then back result to STD_LOGIC:
a,h,f3,f0,k,w,f2,f1 are STD_Logic

Code: 
        a          <= std_logic_vector(to_unsigned((To_integer(unsigned(h)) +
                                                                                 To_integer(unsigned(f3)) + 
                                                                                 To_integer(unsigned(f0)) +
                                                                                 To_integer(unsigned(k)) + 
                                                                                 To_integer(unsigned(w))  + 
                                                                                 To_integer(unsigned(f2)) + 
                                                                                 To_integer(unsigned(f1))),a'length));
 

std_logic but its nature is either 0 or 1.

Do you mean std_logic_vector, furthermore when converting from interger back to std_logic_vector via unsigned you need to specify length
 
FvM said:
Convert to integer makes no sense. Why not add unsigned?
Click to expand...

I tried this:
a <= std_logic_vector(unsigned(h) +unsigned(f3) + unsigned(f0) +unsigned(k) + unsigned(w) + unsigned(f2) + unsigned(f1));

and i still have these errors "Bad expression in left operand of infix expression "+".
(vcom-1078) Identifier "unsigned" is not directly visible.
Illegal type conversion to ieee.std_logic_1164.STD_LOGIC_VECTOR (operand type is not known).
 

"Bad expression in left operand of infix expression "+".
(vcom-1078) Identifier "unsigned" is not directly visible.
Click to expand...

This error is because you have more than one package that declares an unsigned type. You didnt post the code, but I assume you have included std_logic_arith and numeric_std. You should delete std_logic_arith as it is a non-standard VHDL library.

You have another problem: you're trying to convert std_logic to unsigned. Thats impossible, because std_logic is an enumerated type, and unsigned is an array of std_logic. They are not related types.
You will need to make an array out of your single std_logic bits to make them unsigned. There is a nice little hack for this - simply append the bit to a null array. You will also need to qualify the resulting array as unsigned so it doesnt get confused between unsigned and signed:

Code VHDL - [expand]
1

a <= std_logic_vector( unsigned'(""&h) + unsigned(""&f3) ....... etc


Of course, it would have been much easier if a and the other signals were all unsigned in the first place.
 
what libraries are you using?

...you are probably using the ieee.numeric_std along with the conflicting synopsys libraries ieee.std_logic_arith and ieee.std_logic_unsigned.

I've been having a similar problem due to a very old testbench and the need to use some code that requires numeric_std, so I've had to resort to explicitly calling out what functions are used instead of using .all, very annoying.
 
TrickyDicky said:
This error is because you have more than one package that declares an unsigned type. You didnt post the code, but I assume you have included std_logic_arith and numeric_std. You should delete std_logic_arith as it is a non-standard VHDL library.

You have another problem: you're trying to convert std_logic to unsigned. Thats impossible, because std_logic is an enumerated type, and unsigned is an array of std_logic. They are not related types.
You will need to make an array out of your single std_logic bits to make them unsigned. There is a nice little hack for this - simply append the bit to a null array. You will also need to qualify the resulting array as unsigned so it doesnt get confused between unsigned and signed:

Code VHDL - [expand]
1

a <= std_logic_vector( unsigned'(""&h) + unsigned(""&f3) ....... etc


Of course, it would have been much easier if a and the other signals were all unsigned in the first place.
Click to expand...

Thank you so much
It is solved

- - - Updated - - -

ads-ee said:
what libraries are you using?

...you are probably using the ieee.numeric_std along with the conflicting synopsys libraries ieee.std_logic_arith and ieee.std_logic_unsigned.

I've been having a similar problem due to a very old testbench and the need to use some code that requires numeric_std, so I've had to resort to explicitly calling out what functions are used instead of using .all, very annoying.
Click to expand...

Thank you so much
It is solved
 

Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top