Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
What's the circuit model? Schematic looks like distributed RC line, no L, no transmission line effects. If so, what's the motivation for this arbitrary choice? Which real world circuit problem is modelled here?
There should be a difference in impedance levels I think. Like with the CML (Current Mode Logic) circuits, where the logic gates consume DC current to push down output resistance. Parasitic capacitances are the same compared to normal static logic gates, but output resistance is lower, so the time constants are smaller, bandwidth and speed are higher.
If it is coming from a book and isn't explained better I would put down that book.
Voltage and current mode drivers are not one faster than the other inherently. The advantage of voltage mode is that it to produce the same voltage swing it requires lesser current. See for reference: https://www.ece.tamu.edu/~spalermo/ecen689/lecture11_ee689_tx_circuits.pdf
Current mode circuits are faster than voltage mode in general (think of a 1:2 current amplifier) as opposed to a voltage mode amplifier. Your overall speed also depends on the pre-driver stages as well which is often faster in current mode logic.
Suppose the distributed resistance and the distributed capacitance are negligibly small, i.e., assume the wire to be driven is negligibly short. Then the waveform at the driver end of the wire is identical to the waveform at the receiver end of the wire. Negligible delay and negligible rise time degradation.
Since it is given that the wire is driven by a push pull CMOS inverter whose supplies are the digital voltage rails, the waveform at the driver end of the wire (== waveform at receiver too) is a full rail digital signal.
The current mode circuit puts that full rail digital signal through two subcircuits (M1-M4 is the first subcircuit, inverter is the second). The voltage mode circuit puts that full rail digital signal through only one subcircuit (inverter). Therefore voltage mode is faster because it has less delay in the receiver.
Thus we have exhibited a counterexample, in which current mode is slower than voltage mode. Thus "always faster" is false.
Perhaps the thread title should be changed to "voltage mode vs current mode vs matched impedance". Adding termination to the driver cancels the difference between voltage and current mode. You can't see from the outside how the signal is generated, it can be either a voltage source (thevenin equivalent) or current source (Norton equivalent).
In designing a voltage mode, series terminated driver
you have to include the driver's internal resistance
as part of the "Zo" total goal. Since that internal
resistance varies a lot, it must be small, leading to
oversized driver output devices. Which are then a
short circuit protection challenge. One of my first
patents was a short circuit protection scheme for
RS-422 drivers.
Current mode, if controlled by a good reference, is
likely to use smaller drivers and have a high impedance
which in parallel with 50 ohms, you can forget about.
A lot of the speed difference you see, is from transition
from "5V" logic to lower, use of short channel CMOS is
going to bump up speed a lot (and LVDS allows down to
1.8V technology at least, although much remains at 2.5V
and above. Old 5V LVDS was much lower bandwidth (like
150MBPS) than newer parts (400MBPS and higher) with
the main difference being the process node.
This site uses cookies to help personalise content, tailor your experience and to keep you logged in if you register.
By continuing to use this site, you are consenting to our use of cookies.
