how does insertion delay affect timing

Lets say the skew is 0. Does the insertion affect the timing at all in this case?

I would assume it would affect the external signals, but what about timing on internal flop to another internal flop?

The problem here is that your assertion is impossible. Skew is never zero, long gone are the days of zero skew.

The delay of a path on a clock tree, from root to leaf, is the sum of the delay of all gates on that path. The depth of the network, therefore, determines the insertion delay. These gates suffer from process variation. It is therefore possible that one branch of the tree will be very fast while another branch will be very slow, even if they have the same depth. You have to account for the worst case.

What helps is that two flops that are placed next to each other usually have branches that overlap. Say, 80% of the gates on both branches are the same, the difference being on the clock buffers that are very close to the leaf nodes. Being so, your worst case is now relative to the process variation on those gates that are different. The worst case scenario is now not that scary, but still enough to effectively make it impossible to reach zero skew. If skew is not zero, then the delay of the flop-to-flop paths is affected.