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transistor state in cadence vertuso

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Junus2012

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Dear friends, while I am designing CMOS amplifier in cadence vertuso i usually check if the transistor in triode, saturation, cutoff or weal inversion by reading the region from the simulator as follow

region 0 : cutoff
region 1: triode
region 2: satuation
region 3: weak inversion
region 4: breakdown

I know from books that if VDS (sat) is less than 100mV it means the transistor is in weak inversion, but I have many transistors in my design they have like VDS(sat) = 60 mv but the simulator still indicating it as region 2

is the region read from cadence are trustable or not

thank you in advance
 

Dear Junus,
the saturation region depends on the gm over ID ratio that is equal to 2/(VGS-VTH). The weak inversion occours for gm/Id in range 15 - 25 S/A. Probably in your case with 60 mW you don't satisfy this criteria.

BR
 
Trustable, don't use SPICE level 1 equations with BSIM4 models. Low channel devices cannot be modeled with these simple equations. Region function is correct.
 
Thank you guys for your help,

now i will trust the cadence while I am using 1 um channel length, second I need to read about gm/Id method
 

In more realistic models transistors could be in moderate inversion even when the simulator shows that Vgs-Vt<0. As mentioned above, it is really the gm/Id that says when transistor enters the weak inversion region. For example, you can try to plot the gm/Id vs. Vgs or vs. Vgs-Vt and look at what values of Vgs-Vt the curve flattens out.
 
could you guys refer me to an article of how to use the gm/Id in simulation phase or in design,,, i never see it in any analog book

thank you

- - - Updated - - -

Thank you but how to do it by simulation
 

There is a book from last year on the topic
"Systematic Design of Analog CMOS Circuits: Using Pre-Computed Lookup Tables" by Jaspers and Murmann.
Also, if you somehow manage to find Boris Murmann's lectures for EE214B, he talks there about that.
 

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