Design a 4-core processor on FPGA

Hello,

How feasible it is to design a 4-core cpu on a FPGA Spartan 3E. I don't want to design something complicated, but a processor to test a few algorithms, designed for embedded, how fast they can run on FPGA...

Thank you.

It depends how complicated your CPU is....

adwnis123 said:

Hello,

How feasible it is to design a 4-core cpu on a FPGA Spartan 3E. I don't want to design something complicated, but a processor to test a few algorithms, designed for embedded, how fast they can run on FPGA...

Thank you.

Click to expand...

Hello,

the simplest one is "Picoblaze" (Xilinx). It is simple 8-bit CPU:

https://www.xilinx.com/support/documentation/ip_documentation/ug129.pdf

Every instruction is executed in two clock cycles. I tested it on Spartan3A and it can properly works with 180 MHz clock. So one can get 90 MIPS (8-bit data).

You can run four instances of Picoblaze on your FPGA board, but there isn't working 'C compiler' for Picoblaze (you have to program it in assembler).

Ther4e are many free designs of CPU on opencores.org:

https://opencores.org/projects?expanded=Processor

You can also use 32-bit CPus from Xilinx or Intel or Lattice (Microblaze, NIOSII,Mico32). There is also available ARM-CortexM3 as soft-core (but it needs big FPGA to run). For these all 32-bit CPUs are available C compilers.

Regards

The number os cores you can place in a FPGA is directly related to the amount of available logic you have.

So, it really depends of which FPGA you will chose inside 3E family. a XC3S100E hardly will support 4-cores, but a bigger FPGA may support it, depending of the complexity of the core.

Also, there is achoice to be done: if you suport external buses (for example, for parallel flashes, RAM) or will use internal BRAM only. If you use external buses, you increase core complexity. But if you use internal BRAM only you are very limitted regarding code size and RAM memory.

If you are trying to do this for learning purposes, good. But keep in mid you can reuse a core already developed. For example, there are some free cores available on opencores.org. They can be used as reference for your new core as well.

Good luck.

Thank you for your answers. I am looking it....

I want to assign the load to each core, according to a algorithm I have designed. Is it feasible to control each core?

The thing to understand about the FPGA is that you have total freedom over what your cores do (their instructions), their size and how many you have. You could design a turing complete 1 bit core and probably fit 1000 of them running at 200mhz in your spartan. Or you can have one big 32 bit core. That's the flexibility an FPGA offers you (And if you're not doing something special you're probably much better off with a traditional multi-core processor).

I use 500E FPGA. Can I just "copy-paste" the pico-blaze 1-core processor 4 times to make it 4-core and of course configure it, to work properly?

adwnis123 said:

I use 500E FPGA. Can I just "copy-paste" the pico-blaze 1-core processor 4 times to make it 4-core and of course configure it, to work properly?

Click to expand...

Hello,

theoretically yes, but remember that Picoblze program memory is in one of HDL files of your project (VHDL or verilog). It is generated by Picoblaze assembler program.You also should be aware of Input/Output ports of every instance of picoblaze CPU. If your algorithm needs comunication beetwen cores you have to "program" it manually in HDL project.

regards

Something else. How can I find what elements of a processor, does an algorithm take care in order to assign (in multi-core processors) the load to each core?

Thank you.

adwnis123 said:

Something else. How can I find what elements of a processor, does an algorithm take care in order to assign (in multi-core processors) the load to each core?

Thank you.

Click to expand...

Hello,

you have to "program" it in your HDL project. By default each instance of Picoblaze program memory is saved in HDL file. As far as I remember there is also "bootloader" for Picoblaze (in HDL language). So for example you can send code for execution (program) to instance of Picoblaze by UART and execute it. But you have to "program" that all in your FPGA project.

Regards