Recommendations of tools to generate RTL from C/SystemC?

Hello,

My goal is to synthesize RTL in any specific technology library using Design Compiler. However, as you know the implementation of RTL using HDL consumes significant time. Therefore, I would like to explore HLS. I 've been reading about Vivado HLS which has a free version for students, but before going in depth with this tool. My question is, Can I use the generated RTL from Vivado, and use it in Design Compiler instead of a FPGA? or is there any other HLS tool available for students that generates RTL from C and I can use it with Design Compiler, that you recommend?

Thanks

However, as you know the implementation of RTL using HDL consumes significant time.

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So...you tried learning HDL, had great success with it - but after many years of experience your'e looking for something to accelerate your design process ?

My question is, Can I use the generated RTL from Vivado, and use it in Design Compiler instead of a FPGA?

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If there are no Xilinx primitives in the generated RTL, then theoretically DC should not be complaining.

or is there any other HLS tool available for students that generates RTL from C and I can use it with Design Compiler, that you recommend?

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I don't think so. Mostly the big shot EDA companies have such tools and they do not have a student version. But check them out yourself.
Mentor has such a tool as far as I know.

shaiko said:

So...you tried learning HDL, had great success with it - but after many years of experience your'e looking for something to accelerate your design process ?

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I do believe that HLS is more efficient in terms of Datapath design, and also it would give much better flexibility to explore multiple desigs. Considering that, yes I am looking for something that can help with that in less time, even if I am not an expert with HDL.

Don't get me wrong - I think HLS is great. And if major improvements continue it may become the future...
What I don't like is the way HLS is being marketed sometimes.
As a tool to widen the user base from hardware engineers (that understand the underlining architecture and it's limitations) to anyone who can write a line of code in C.

I believe that to be a good professional logic designer (regardless of your chosen design entry method) you have to first get your hands dirty with HDL (at least for 2-3 years).
Otherwise, a generation of mediocre engineers will grow that treat these HLS compilers as "black magic machines".
The same happened in software...

I believe that to be a good professional logic designer (regardless of your chosen design entry method) you have to first get your hands dirty with HDL (at least for 2-3 years).

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Can't agree more!

Don't listen to the Xilinx marketing guys propaganda.