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Problem measuring output impedance of CMOS inverter using ngspice

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promach

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Cross posting from https://sourceforge.net/p/ngspice/discussion/133842/thread/f1d04424/?limit=25#6896

Why am I getting negative output impedance using the following test circuit ?

Code: 
*CMOS inverter 

.PARAM V_SUPPLY = 3.3
.PARAM V_OUT = 2
*.PARAM INP_FREQ = '#INP_FREQ#'
*.PARAM INP_PERIOD = '1/INP_FREQ'
*.PARAM NO_PERIODS = '4'
*.PARAM TMEAS_START = '(NO_PERIODS-1)*INP_PERIOD'
*.PARAM TMEAS_STOP = '(NO_PERIODS)*INP_PERIOD'
.PARAM AC_POINTS = 10
.PARAM AC_START = 1000
.PARAM AC_STOP = 1E6

*** *** SUPPLY VOLTAGES *** ***
VDD VDD 0 'V_SUPPLY'
VSS VSS 0 0

*** *** INPUT SIGNAL *** ***
VSIG IN VSS AC 1 DC 1

*** *** CIRCUIT UNDER TEST *** ***
MP OUT IN VDD VDD P1 W=0.07963 L=0.001 
MN OUT IN VSS VSS N1 W=0.03982 L=0.001 

** CL OUT VSS 3p
RIN IN VSS 1G

Rf OUT IN 0.01
** The input can be either biased with a DC source, or a DC feedback circuit. Using a DC feedback circuit (RC, inductor, whatsoever) makes only sense if there's no DC voltage source, see https://www.edaboard.com/showthread.php?377214-Noise-in-CMOS-Inverter&p=1617292&viewfull=1#post1617292  

*** *** ROUT TEST SIGNAL WITH FIXED 1A CURRENT AND VARIABLE TEST VOLTAGE (VOUT) *** ***
*VOUT VOUT 0 'V_OUT'
IOUT OUT VSS AC 1 DC 1

*** *** ANALYSIS *** ***
*.AC dec 'AC_POINTS' 'AC_START' 'AC_STOP'
*.TRAN 'INP_PERIOD/1000' 'NO_PERIODS*INP_PERIOD'
*
*.PROBE TRAN V(IN)
*.PROBE TRAN V(OUT)
.OPTION POST PROBE ACCURATE
.include modelcard.nmos
.include modelcard.pmos

.control
*AC dec 'AC_POINTS' 'AC_START' 'AC_STOP'
AC dec 10 1000 1E6

let ROUT=OUT/(i(Vss))
plot ROUT
print ROUT > ROUT.log
.endc

.END

MY0w4ZB.png
 

There may be other faults, but you have two AC sources activated simultaneously, VSIG and IOUT. This way you don't measure output impedance.
 
I think this depends on the direction of i(Vss), which probably is negative.
BTW: i(Vss) probably contains all currents into VSS, i.e. also those of the pre-stages.

I'd suggest you better use an ROUT definition like
Code: 
let ROUT=OUT/(i(OUT))
... and care for the correct output condition (usually short circuit). Use a very small resistor (like your Rf) connected from output to VSS via a huge capacitor.
 

two AC sources activated simultaneously, VSIG and IOUT.
Click to expand...

@FvM

What do you suggest then ?

- - - Updated - - -

See the resulting frequency response when I short the CMOS inverter input to ground, literally means that I only have one AC source in the test circuit.

Code: 
*CMOS inverter 

.PARAM V_SUPPLY = 3.3
.PARAM V_OUT = 2
*.PARAM INP_FREQ = '#INP_FREQ#'
*.PARAM INP_PERIOD = '1/INP_FREQ'
*.PARAM NO_PERIODS = '4'
*.PARAM TMEAS_START = '(NO_PERIODS-1)*INP_PERIOD'
*.PARAM TMEAS_STOP = '(NO_PERIODS)*INP_PERIOD'
.PARAM AC_POINTS = 10
.PARAM AC_START = 1000
.PARAM AC_STOP = 1E6

*** *** SUPPLY VOLTAGES *** ***
VDD VDD 0 'V_SUPPLY'
VSS VSS 0 0

*** *** INPUT SIGNAL *** ***
VSIG IN VSS 0

*** *** CIRCUIT UNDER TEST *** ***
MP OUT IN VDD VDD P1 W=0.07963 L=0.001 
MN OUT IN VSS VSS N1 W=0.03982 L=0.001 

** CL OUT VSS 3p
RIN IN VSS 1G

Rf OUT IN 0.01
** The input can be either biased with a DC source, or a DC feedback circuit. Using a DC feedback circuit (RC, inductor, whatsoever) makes only sense if there's no DC voltage source, see https://www.edaboard.com/showthread.php?377214-Noise-in-CMOS-Inverter&p=1617292&viewfull=1#post1617292  

*** *** ROUT TEST SIGNAL WITH FIXED 1A CURRENT AND VARIABLE TEST VOLTAGE (VOUT) *** ***
*VOUT VOUT 0 'V_OUT'
IOUT OUT VSS AC 1 DC 1

*** *** ANALYSIS *** ***
*.AC dec 'AC_POINTS' 'AC_START' 'AC_STOP'
*.TRAN 'INP_PERIOD/1000' 'NO_PERIODS*INP_PERIOD'
*
*.PROBE TRAN V(IN)
*.PROBE TRAN V(OUT)
.OPTION POST PROBE ACCURATE
.include modelcard.nmos
.include modelcard.pmos

.control
*AC dec 'AC_POINTS' 'AC_START' 'AC_STOP'
AC dec 10 1000 1E6

let ROUT=OUT/(i(VSS))
plot ROUT
print ROUT > ROUT.log
.endc

.END

Screenshot from 2018-07-04 11-42-00.png
 
Shorting input to ground is neither correct, you want DC bias but no AC source.

Getting still negative impedance points to a sign error, as already mentioned by erikl. Seriously I don't understand the reasoning behind
ROUT=OUT/(i(VSS))

Why I(Vss)? If you send 1 A to the output, the output impedance is equal to V(out).
 

Anyone have comment about the following simulation result ? I am going to double check against manual maths calculation ?

FSe5Anc.png


Code: 
*CMOS inverter 

.PARAM V_SUPPLY = 3.3
.PARAM V_OUT = 2
*.PARAM INP_FREQ = '#INP_FREQ#'
*.PARAM INP_PERIOD = '1/INP_FREQ'
*.PARAM NO_PERIODS = '4'
*.PARAM TMEAS_START = '(NO_PERIODS-1)*INP_PERIOD'
*.PARAM TMEAS_STOP = '(NO_PERIODS)*INP_PERIOD'
.PARAM AC_POINTS = 10
.PARAM AC_START = 1000
.PARAM AC_STOP = 1E6

*** *** SUPPLY VOLTAGES *** ***
VDD VDD 0 'V_SUPPLY'
VSS VSS 0 0

*** *** INPUT SIGNAL *** *** set Vgs manually such that both mosfets are at saturation 
VSIG IN VSS AC 1 DC 'V_SUPPLY/2'

*** *** CIRCUIT UNDER TEST *** ***
MP OUT IN VDD VDD P1 W=2U L=2U
MN OUT IN VSS VSS N1 W=1U L=2U 

** CL OUT VSS 3p
** RIN IN VSS 1G

** CIN IN VSS 111
** Rf OUT IN 0.01
** The input can be either biased with a DC source, or a DC feedback circuit. Using a DC feedback circuit (RC, inductor, whatsoever) makes only sense if there's no DC voltage source, see https://www.edaboard.com/showthread.php?377214-Noise-in-CMOS-Inverter&p=1617292&viewfull=1#post1617292  


*** *** ROUT TEST SIGNAL WITH FIXED 1A CURRENT AND VARIABLE TEST VOLTAGE (VOUT) *** ***
*VOUT VOUT 0 'V_OUT'
*** *** IOUT flows into the output of the circuit under test, so negative terminal node of this current source is OUT instead of VSS
IOUT VSS OUT AC 1

*** *** ANALYSIS *** ***
*.AC dec 'AC_POINTS' 'AC_START' 'AC_STOP'
*.TRAN 'INP_PERIOD/1000' 'NO_PERIODS*INP_PERIOD'
*
*.PROBE TRAN V(IN)
*.PROBE TRAN V(OUT)
.OPTION POST PROBE ACCURATE
.include modelcard.nmos
.include modelcard.pmos

.control
*AC dec 'AC_POINTS' 'AC_START' 'AC_STOP'
AC dec 10 1000 1E6

let ROUT=OUT/abs(i(VSS))
plot ROUT
print ROUT > ROUT.log
.endc

.END
 

The input can be either biased with a DC source, or a DC feedback circuit. Using a DC feedback circuit (RC, inductor, whatsoever) makes only sense if there's no DC voltage source
Click to expand...
Don't agree. It makes particularly sense if you want to guarantee that the circuit is biased in active range (both transistors in saturation) without tuning a DC voltage.

But my point was different. You must not place a second AC source along with the bias circuit. Your latest post clarifies that you still have. Whatever the latest plot shows, it can't be output impedance.

Code: 
VSIG IN VSS [COLOR="#FF0000"]AC 1[/COLOR] DC 'V_SUPPLY/2'

I'm outty
 

An inverter's output impedance will change with common
mode output position and with input bias. You can't really
have both transistors of a standard CMOS inverter in the
saturation region, at once, because the gates are co-driven.
The Zout will also have a Miller element at higher frequencies
which makes Zo have a parallel gain, Zin dependent term.
So you want to represent the gate drive reasonably.

If you are operating large signal then the output impedance
will be constantly changing and small signal analysis is not
your friend, you might want a PSS or other transient based
analysis to get a Zout. Though it looks like your analysis
does not extend to "real RF".

A replica biasing scheme might serve you if you want the
output at VDD/2 for analysis; one inverter shorting out:in,
and use that voltage for the gate of the second as well.
Ideal matching in the simulator will make the test inverter
output go to VDD/2 as well.
 

You must not place a second AC source along with the bias circuit.
Click to expand...

@FvM

Could you justify why ?
 

Both sources are acting simultaneously, the output voltage you are measuring is caused by the superposition of both, but you want to see only the effect of injected output current.

That's just elementary electrical network theory, I believe.
 

No matter how I measure the output impedance, the result can never come any close to the following theoretical calculation

https://github.com/imr/ngspice/blob/master/examples/xspice/table/modelcards/modelcard.pmos

LxKjmWR.png
CJWRtiG.png


Code: 
*CMOS inverter 

.PARAM V_SUPPLY = 3.3
.PARAM V_OUT = 2
*.PARAM INP_FREQ = '#INP_FREQ#'
*.PARAM INP_PERIOD = '1/INP_FREQ'
*.PARAM NO_PERIODS = '4'
*.PARAM TMEAS_START = '(NO_PERIODS-1)*INP_PERIOD'
*.PARAM TMEAS_STOP = '(NO_PERIODS)*INP_PERIOD'
.PARAM AC_POINTS = 10
.PARAM AC_START = 1000
.PARAM AC_STOP = 1E6

*** *** SUPPLY VOLTAGES *** ***
VDD VDD 0 'V_SUPPLY'
VSS VSS 0 0

*** *** INPUT SIGNAL *** *** 
VSIG IN VSS 0
** VSIG IN VSS AC 1 DC 'V_SUPPLY/2'

*** *** CIRCUIT UNDER TEST *** ***
MP OUT IN VDD VDD P1 W=2U L=2U
MN OUT IN VSS VSS N1 W=1U L=2U 

** CL OUT VSS 3p
** RIN IN VSS 1G

CIN IN VSS 1E9
Rf OUT IN 1E9
** Lf OUT IN 1E-12
** The input can be either biased with a DC source, or a DC feedback circuit. Using a DC feedback circuit (RC, inductor, whatsoever) makes only sense if there's no DC voltage source, see https://www.edaboard.com/showthread.php?377214-Noise-in-CMOS-Inverter&p=1617292&viewfull=1#post1617292  


*** *** ROUT TEST SIGNAL WITH FIXED 1A CURRENT AND VARIABLE TEST VOLTAGE (VOUT) *** ***
*VOUT VOUT 0 'V_OUT'
*** *** IOUT flows into the output of the circuit under test, so negative terminal node of this current source is OUT instead of VSS
IOUT VSS OUT AC 1

*** *** ANALYSIS *** ***
*.AC dec 'AC_POINTS' 'AC_START' 'AC_STOP'
*.TRAN 'INP_PERIOD/1000' 'NO_PERIODS*INP_PERIOD'
*
*.PROBE TRAN V(IN)
*.PROBE TRAN V(OUT)
.OPTION POST PROBE ACCURATE
.include modelcard.nmos
.include modelcard.pmos

.control
*AC dec 'AC_POINTS' 'AC_START' 'AC_STOP'
AC dec 10 1000 1E6

let ROUT=OUT/abs(i(VSS))
plot ROUT
print ROUT > ROUT.log
.endc

.END
 
Last edited:

Do you see the bold text "(valid in the saturation region)"?

Do you see that in an inverter one, the other or both
devices -will not- be in saturation under any condition?

And if they both were, the fact of -two- FET conductances
in drain-parallel would be some kind of error term relative
to that single-transistor formula.
 

See https://electronics.stackexchange.com/questions/383552/measurement-of-output-impedance-of-a-cmos-inverter

Code: 
*CMOS inverter https://electronics.stackexchange.com/questions/383552/measurement-of-output-impedance-of-a-cmos-inverter

.PARAM V_SUPPLY = 3.3
.PARAM V_OUT = 2
*.PARAM INP_FREQ = '#INP_FREQ#'
*.PARAM INP_PERIOD = '1/INP_FREQ'
*.PARAM NO_PERIODS = '4'
*.PARAM TMEAS_START = '(NO_PERIODS-1)*INP_PERIOD'
*.PARAM TMEAS_STOP = '(NO_PERIODS)*INP_PERIOD'
.PARAM AC_POINTS = 10
.PARAM AC_START = 1000
.PARAM AC_STOP = 1E6

*** *** SUPPLY VOLTAGES *** ***
VDD VDD 0 'V_SUPPLY'
VSS VSS 0 0

*** *** INPUT SIGNAL *** *** 
** VSIG IN VSS 0
** VSIG IN VSS AC 1 DC 0
** VSIG IN VSS AC 1 DC 'V_SUPPLY/2'

*** *** CIRCUIT UNDER TEST *** ***
MP OUT IN VDD VDD P1 W=2U L=2U
MN OUT IN VSS VSS N1 W=1U L=2U 

** CL OUT VSS 3p
** RIN IN VSS 1G

CIN IN VSS 1
Rf OUT IN 1E15
** Lf OUT IN 1E-15
** The input can be either biased with a DC source, or a DC feedback circuit. Using a DC feedback circuit (RC, inductor, whatsoever) makes only sense if there's no DC voltage source, see https://www.edaboard.com/showthread.php?377214-Noise-in-CMOS-Inverter&p=1617292&viewfull=1#post1617292  


*** *** ROUT TEST SIGNAL WITH FIXED 1A CURRENT AND VARIABLE TEST VOLTAGE (VOUT) *** ***
*VOUT VOUT 0 'V_OUT'
*** *** IOUT flows into the output of the circuit under test, so negative terminal node of this current source is OUT instead of VSS
IOUT VSS OUT AC 1

*** *** ANALYSIS *** ***
*.AC dec 'AC_POINTS' 'AC_START' 'AC_STOP'
*.TRAN 'INP_PERIOD/1000' 'NO_PERIODS*INP_PERIOD'
*
*.PROBE TRAN V(IN)
*.PROBE TRAN V(OUT)
.OPTION POST PROBE ACCURATE
.include modelcard.nmos
.include modelcard.pmos

.control
*AC dec 'AC_POINTS' 'AC_START' 'AC_STOP'
AC dec 10 1000 1E6

let ROUT=OUT/abs(i(VSS))
plot ROUT
print ROUT > ROUT.log
.endc

.END
 

You have 
Code VHDL - [expand]
1

IOUT VSS OUT AC 1

so try 
Code VHDL - [expand]
1

let ROUT=V(OUT)

... as FvM told you in post #5 .
 

The following is my updated test circuit. However, using your advice give me lower output impedance, about 8 kilo ohms lower compared to theoretical calculation. I am still very doubtful about the correctness of test circuit setup for output impedance measurement.

Code: 
*CMOS inverter https://electronics.stackexchange.com/questions/383552/measurement-of-output-impedance-of-a-cmos-inverter

.PARAM V_SUPPLY = 3.3
.PARAM V_OUT = 2
*.PARAM INP_FREQ = '#INP_FREQ#'
*.PARAM INP_PERIOD = '1/INP_FREQ'
*.PARAM NO_PERIODS = '4'
*.PARAM TMEAS_START = '(NO_PERIODS-1)*INP_PERIOD'
*.PARAM TMEAS_STOP = '(NO_PERIODS)*INP_PERIOD'
.PARAM AC_POINTS = 10
.PARAM AC_START = 1000
.PARAM AC_STOP = 1E6

*** *** SUPPLY VOLTAGES *** ***
VDD VDD 0 'V_SUPPLY'
VSS VSS 0 0

*** *** INPUT SIGNAL *** *** 
** VSIG IN VSS 0
** VSIG IN VSS AC 1 DC 0
** VSIG IN VSS AC 1 DC 'V_SUPPLY/2'

*** *** CIRCUIT UNDER TEST *** ***
MP OUT IN VDD VDD P1 W=2U L=2U
MN OUT IN VSS VSS N1 W=1U L=2U 

** CL OUT VSS 3p
** RIN IN VSS 1G

CIN IN VSS 1
Rf OUT IN 1E15
** Lf OUT IN 1E-15
** The input can be either biased with a DC source, or a DC feedback circuit. Using a DC feedback circuit (RC, inductor, whatsoever) makes only sense if there's no DC voltage source, see https://www.edaboard.com/showthread.php?377214-Noise-in-CMOS-Inverter&p=1617292&viewfull=1#post1617292  


*** *** ROUT TEST SIGNAL WITH FIXED 1A CURRENT *** ***
** this is a way to measure or plot the current source IOUT in spice using 0V voltage source
VOUT OUT VOUT 0
*** *** IOUT flows into the output of the circuit under test, so negative terminal node of this current source is OUT instead of VSS
IOUT VSS VOUT AC 1

*** *** ANALYSIS *** ***
*.AC dec 'AC_POINTS' 'AC_START' 'AC_STOP'
*.TRAN 'INP_PERIOD/1000' 'NO_PERIODS*INP_PERIOD'
*
*.PROBE TRAN V(IN)
*.PROBE TRAN V(OUT)
.OPTION POST PROBE ACCURATE
.include modelcard.nmos
.include modelcard.pmos
** https://github.com/imr/ngspice/blob/master/examples/xspice/table/modelcards/modelcard.nmos
** https://github.com/imr/ngspice/blob/master/examples/xspice/table/modelcards/modelcard.pmos

.control
*AC dec 'AC_POINTS' 'AC_START' 'AC_STOP'
AC dec 10 1000 1E6

let ROUT=v(OUT)/abs(i(VOUT))
plot ROUT
print ROUT > ROUT.log
.endc

.END
 

The test circuit should basically work. Rf may be a way too high if the MOSFETs show leakage current. 1e9 should be more than suffcient. Check the bias point!
 
Rf may be a way too high if the MOSFETs show leakage current.
Click to expand...

Why if I decrease Rf from 1E15 to 1E9 , ROUT increases from 48.563 kohm to 48.5705 kohm

Check the bias point!
Click to expand...

This is a self-bias CMOS inverter. Could you advise ?
 

promach said:
... using your advice give me lower output impedance, about 8 kilo ohms lower compared to theoretical calculation. 
Code VHDL - [expand]
1

Rf OUT IN 1E15
Click to expand...
... generates a (nearly) full feedback amplifier, i.e. gain≈1 for low frequencies (LF), with corresponding low LF output impedance. Did you consider this?
 

... generates a (nearly) full feedback amplifier, i.e. gain≈1 for low frequencies (LF), with corresponding low LF output impedance.
Click to expand...
Not in the frequency range of interest with 1F filter capacitor!


Why if I decrease Rf from 1E15 to 1E9 , ROUT increases from 48.563 kohm to 48.5705 kohm
Click to expand...
You didn't tell before how much the expected value is. 20% deviation sounds realistic.

This is a self-bias CMOS inverter. Could you advise ?
Click to expand...
Means check the bias resistor voltage drop. Apparently it's acceptable. That's it.
 

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