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[SOLVED] Synthesize an RTL from two technology .db files (of same node)

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ranaya

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Hi All,

I have a requirement of synthesizing an RTL code in which, some of the gates should be synthesized from a generic standard cell library (i.e. tsmc 90nm) and one or two from my own library (characterized and custom made around the same 90nm pdk). If both library files are available in .db format, can we do it in a standard compiler like synopsys dc ? Or should I have to integrate my .db with the generic one (But I suppose this is not possible as the generic one is not open access) ?

Thanks in advance
Anuradha
 

Yes, you can. Just specify both libraries in target_library of DC. (set target_library "aaa.db bbb.db")
 

Hi, thanks for the response. Now suppose that both .dbs have an inverter gate which matches the behavior RTL "~" operation. How can I blacklist a the inverter of the std_cell, and make the tool (i.e. design compiler) to pick the one in my .db ?

Anuradha

PS : both should be in target_library or link_library ?
 

ranaya said:
Hi, thanks for the response. Now suppose that both .dbs have an inverter gate which matches the behavior RTL "~" operation. How can I blacklist a the inverter of the std_cell, and make the tool (i.e. design compiler) to pick the one in my .db ?

Anuradha

PS : both should be in target_library or link_library ?
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Say that again? I can't understand what you are trying to do.
 

You can mark particular cells with set_dont_use command.

It's safely to have:
set link_library "* $target_library other.db"
 
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Hi, thanks all.

@oratie : That is what I was looking for. Thanks !
 

you could also use set_dont_use on specific cell.
 
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