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Need help on level shifter

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richloo

richloo

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Can u guyz explain the operation of the circuit shown below. Especially the cross paired pmos. Thanks in advance!
 

The action is quite simple.

Case I
====
When there is a zero at the input of inverter of Low VDD,
there is
1 - at the output of inverter
0 - at the drain of the right hand side NMOS device at high VDD
1 - at the drain of the left hand side NMOS device at high VDD( because the PMOS sees a 0 and conducts VDD)

Then the output is inverted from there causing a "0" at the output

Case II
=====
When there is a 1 at the input of the inverter of Low VDD,
there is
1 -at the gate of left hand side NMOS at High VDD
0 - at the drain of left hand side NMOS at High VDD
1- at the output of inverter at High VDD

I hope that it is clear.....I am attaching the picture in both the cases
 

    richloo

    richloo

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Thanks Vamsi, good explaination. However, i feel difficulty in the design, especially the cross paired pmos and the nmos input at the output of low voltage inverter. Can anyone comment on the transient aspect of designing a high speed level shifter base on this circuit? Thanks in advance!
 

The PMOS's w/l should be small and the NMOS's w/l should be large. If you want to deisgn high speed level shift, the length of PMOS and NMOS should be small. The ratio of NMOS's w/l to PMOS's w/l depend on the voltage difference of the low voltage and the high voltage. You can use SPICE's optimize function to design it.
 

bear7679 said:
The PMOS's w/l should be small and the NMOS's w/l should be large. If you want to deisgn high speed level shift, the length of PMOS and NMOS should be small. The ratio of NMOS's w/l to PMOS's w/l depend on the voltage difference of the low voltage and the high voltage. You can use SPICE's optimize function to design it.
Click to expand...

thanks bear, i realize that large nmos is to drive the input from low voltage faster. How about the function of pmos cross paired? As u mentioned, the ratio of nmos and pmos is dependent on the voltage level. Are u telling me that i need to adjust the DC of the o/p (before the o/p inverter) to half of VccHi?

Regards
 

the paired PMOS here are used to prevent the current from HIVDD to GND when
the pmos & nmos ON simultaaneouslly for it leads to large power dessipation.
So when design a Level-Shifter, you should insure once the nmos at the output of low voltage inverter ON, the upper PMOS whould be OFF immediately. Due to the lov voltage of LVDD, the W/L of the nmos should be large while the W/L of PMOS should be small.When design this, u should first run DC simulation, and then run Tran simulation.
 

    richloo

    richloo

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Actually, I am designing this for robustness (PVT) and as a reusable block. Thanks, I have met the spec using the method by aken_lu. However, I found difficulty on having a symmetrical performance, i.e. risetime, falltime, delayrise, delayfall during PVT variation since it is single ended. Can anyone comment on this? Thanks in advance.
 

probe all output nodes and play around the p/n ratio
 

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