Digital VLSI verification engineer - required knowledge

Hello everyone,
I am a junior digital IC designer and i've being thinking of transitioning to the verification field.
What are the requirements for such a transition? Are there any common fields between digital verification and design ( common knowledge etc? )
And how close is verification to IC design? From my point of view, it seems closer to software engineer ( scripting etc ) than to hardware design?

Thank you in advance,
Nikos

Hello,

This is a very general answer to your specific question from a verification engineer.
If you want to find what kind of skill set is required for a job I'd suggest start by looking at the openings in various job portals. look for various job descriptions and understand the keywords mentioned repeatedly. Although what you said about verification being perceived as closer to software than hardware is somewhat true from my experience having hardware design background certainly helps.

Hope this helps.

BR, Kishor.

Thank you for your answer.
So learning a high-level programming language is a must? Is Systemverilog enough for verification? And how difficult is the transition from HDL language to a high-level one?

thank you!

What are the requirements for such a transition?
- You need to study logic function of basic standard cell : It is for gate level simulation
- You need to study Simulation EDA tool, how it works, how to make a verification environment.
- How to make a test pattern, how to confirm them as good or bad. It is quite new things to IC designers.

Are there any common fields between digital verification and design ( common knowledge etc? )
- Design flow would be important. You will know the relationship and in/out data.

And how close is verification to IC design?
- Very different.

From my point of view, it seems closer to software engineer ( scripting etc ) than to hardware design?
- No. It is hardware design.
Scripting is used like utility, improve the efficiency.
Using software mindset on hardware design will cause a big mess. It is a headache.

Thank you slutarius, your answers are very insightfull.
Just a clarification on the last question/answer : Verification languages , such as SV for verification, are high level object-oriented language right? So,mostly i will be using "software coding" rather than "hardware/rtl coding"

Yes. SV is like verilog + object-orientation language.
So both knowledge are required.

That clears it up, thank you again!

Verification is not software style job. You will need to understand architecture of your design and come up with test plans to find bugs in new features coded by design team. You should be able to run EDA tools like VCS, Verdi, etc to run your test vectors and finally debug and find a bug. There are lot of domains which are similar to design flow, however, only difference is you are not creating any content in design. You are validating if RTL is behaving correctly as required by architecture team.

Thanks,
Abhishek